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Aren't markers thrown, that you can display to

find the offenders and interrogate them?

I believe it's possible to "do things" to or above

placed stdcell instances, which will "fool" DRC

into identifying them as high voltage (vanilla logic

always gets the basic layout, with later extensions

getting "marked").

Look at (if you can) the specific rule logic - its

input terms should inform you the layers at play

and look for the one that has no business in a

low voltage logic gate. Process of elimination

may get you there. Or at least narrow the field

for you to go hunting polygons.

Like, somebody could have thrown a "HVmark"

rectangle over the whole chip (like you probably

place "bulk") when it should have been "surgical"

around some pads or something. Be sure to look

down from top level from funky layers, they may

(should) not be in with the logic itself. But maybe

your logic is part of a block with HV content and

got "over-marked" by a layout person who knew

"it's a HV block" and nothing more.

I don't know what a HiR resistor's construction is.

If it's a very shallow very light implant sitting in a

HV well, maybe it's the well than needs marked

and not the resistor body. Or something. There

should be a PDK groundrule document that says

how it should be made; again, turn off every legit

layer for that device and see what's left. Or, when

you went to turn off a layer that should have been

there and no difference, see if that is part of rule

logic (incl precursors).

I don't work with TSMC so specifics, you'll have to

get elsewhere. Stepped in stuff before, though, yeah.