LTspice...splitting LT1243 output into two separate pulse streams

[treez]

Hi,
I wish to simulate a Half Bridge SMPS in LTspice, but using the LT1243 adapted to control it.
I need to split the gate drive in to two separate streams as in the attached.
Would you say D flip flop for each stream would be best to achieve these two streams?

(LTspice sim also attached)

 

[wwfeldman]

please show how you want to connect/use the D FF

i expect you'll need to connect the current sense

i would suggest a half bridge controller, maybe even with a high side driver built in
maybe a TI LM5039 - don't know if it meets your requirements, but it is more in line
with a half bridge

 

[treez]

Thanks, this is purely sim and we wish to use the LT1243 as its so quik and eazy to use.

The attached (LTspice and schem) shows how it can be done…but I am getting an unfortunate little spike in the waveform streams as shown.
Any better ways?

 

[wwfeldman]

the rising edge of the LT1243 clocks the DFF, s both transistors "switches" are on at the same time -
one turning on and one turning off

shouldn't QQQ and QNOT go to the switch controls, SSS and TTT,
with the sources B1 and B2 going to the business part of the switches?

not familiar with the control V=(V(QQQ)-1)
when V(QQQ) = 0, does V=(V(QQQ)-1) give a -1?

 

[treez]

not familiar with the control V=(V(QQQ)-1)
when V(QQQ) = 0, does V=(V(QQQ)-1) give a -1?

Thanks, yes, i have to get "-1" because the switch only responds to "+1" and "-1" for "ON" and "OFF" respectively

the rising edge of the LT1243 clocks the DFF, s both transistors "switches" are on at the same time -
one turning on and one turning off

Yes i think i need a delay to sort this out...but delays dont seem to be covered in the manual for ltspice

 

[KlausST]

Hi,

but I am getting an unfortunate little spike in the waveform streams as shown.

use an inverter in front of the DFF_CLK_Input. .. to clock the DFF at the falling edge of U1_ouput.
The additional delay gives extra relaxed timing.


Klaus

 

[wwfeldman]

maybe a part designed to do what you want
rather than forcing a square peg into a round hole

if you want to build this, you'll need to add a variety of hardware to make it work
including high and low side gate drivers, guaranteed off time (assuming it is voltage fed)
etc

 

[treez]

Thanks , this is purely for sim purposes to look at checking sims for the transformer turns checking.

Thankyou Klaus you are a genius as always!...added your inverter, and now no spike.

 

[FvM]

There seems to be a "small" problem. LT1243 is a current mode controller. As far as I understand, there's no way to generate pwm output without using the current sense input, which isn't feasible with half bridge.

 

[treez]

Thanks yes thats right......but i can put a ramp into the Current sense input from the clock pin....and thus do it in voltage mode.....with some resistance in there for current limiting in case of short circuit.

In fact, though in real life a half bridge can't be done in current mode......in the simulator, it actually works.

 

[asdf44]

You're just driving a half bridge from a signle PWM output and need to insert dead time?

Why not use the age old R+diode circuit. Add an R for turn on which is bypassed by a diode for instant turn off. Use LTSpice logic gates to buffer this stuff if you want.


Another strategy I use is to skip the fets or switches altogether and simulate the output of the half bridge with a dependent source. If the gate drive signal is 5V and your half bridge is 50V I make a source where Vout=V(gate_drive)*10. It's often useful when focusing on topology or control.