LTspice snubber simulations dont seem incorrect?

because a sim is always markedly different to the real world at higher powers ....

Ignore Ep's flip answer.

Can you post the .asc file?

Can you post the .asc file?

Click to expand...

....Thats the .asc file in the top post, zipped up, the "attach link" wont take .asc files if not zipped.

I am actually wondering that the sim model of the FET does not account for the great reduction in Cds as Vds rises, and maybe thats why my fet blew up on the bench, since there was less capacitance than i thought to quell the drain node ringing.

I believe next time i power up this 1000w boost pfc, i will use only a 10uf cout, and a 1200v igbt, and a max duty cycle of 0.54 (thats as low as you cam make the max with ucc28070a)....and again only load it to 7W.

Another problem may be the distance i have from the 50:1 CST to the controller. Its a toss up whether to have the burden resistor near the CST , or near the controller....and whether to make the layout more complex by having dedicated "star" tracks from the CST to the burden resistor......thing is, the final cct is for 4 Boosters interleaved, so i want to keep the layout as simple as possible, as far as possible.

You can easily measure model capacitance. LTspice MOSFET model is using a simple function with few parameters and doesn't exactly model the capacitance according to datasheet exactly, but it gives at least a typical non-linear capacitance characteristic, see below. For better capacitance modelling you should refer to vendor models as provided e.g. by ST or Wolfspeed. Don't know if Rohm has it.

Total switching branch stray inductance should be rather in a 10 to 20 nH than several 100 nH order of magnitude, unless the PCB layout is really bad. Thus I doubt your simulation is realistic.