LTSpice Simulation

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KronosX

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Hello,

I need help in plotting the output current vs the drain voltage from 0 to 10 Volts.
I'm not sure what am I doing wrong with my simulation.
I added the width and length of all transistors and set the model to match the parameters specified.







 

Hi,

Looking at the diagrams, a few things I have noticed:

*You have substituted MOSFETs for JFETs.
*Iout and I'out are two different variables but you have tied them together and given them the name Iout.

Correct these, try again and let us know the result.
 

You have substituted MOSFETs for JFETs.
Don't think so. All transistors have insulated gate, no JFETs. Just strange circuit drawing style. Substrate connection is only explicitely shown for transistors with floating source.

Fault is measuring difference current Iout - Iout' instead of Iout, as stated.

Don't know why M9 has been removed.
 

Hello,

I substituted jfets for mosfets and used "COM" to split Iout and I'out. Using two different output ports was giving me no current.
I'm still not satisfied with the results since they should match my theoretical results. Any ideas?

Thanks.

 

The problem starts at the bias node R2 / M10, which the follower
NMOS M9 soaks up with its VT so nothing left for the rest
(M1, M2).

Try stacking another nmos between M10 and GND.
 
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    d123

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Don't think so. All transistors have insulated gate, no JFETs. Just strange circuit drawing style. Substrate connection is only explicitely shown for transistors with floating source.
Yes, I have realised it. The parameters in the questions are for MOSFETs.
--- Updated ---

Hello,

I substituted jfets for mosfets and used "COM" to split Iout and I'out. Using two different output ports was giving me no current.
You're basically still having M5 and M6 connected in series.
You might need to connect a suitable load to do the current measurement.
 
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Also, considering the parameters, how have you considered W/L, phi, and gamma?
 

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