DanyR
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LTSpice IV, curious simulation problems
Hi, I encountered some curious simulation problem when simuating this circuit:

View attachment Inverter_6_stability.txt
Plot file: View attachment Inverter_6_stability.plt.txt
The error during simulation is (almost always) something like this:
while there is nothing wrong with the nodes named,and also the named nodes or op-amps can differ after I changed something completely unrelated to the circuit.
Also sometimes the error "... step too small" occurs.
Anyone any suggestions?
Thanks in advance!
Hi, I encountered some curious simulation problem when simuating this circuit:

View attachment Inverter_6_stability.txt
Plot file: View attachment Inverter_6_stability.plt.txt
The error during simulation is (almost always) something like this:

Also sometimes the error "... step too small" occurs.
Anyone any suggestions?
Thanks in advance!