LT6119-1 sens amplifier chip logic question

[yefj]

Hello, I am trying to understand the sense amplifier chip implementation for biasing IRF9640.
We have 12V going to the source of a PMOS IRF9640.
Regarding the LE PIN- as seen in the data sheet below we have RC connection.
RC circuit is exponential rise of voltage but in the data sheet they say that we need to keep it high for output latch.
but with gradual increase it will be somewhere in the middle?.
How this RC circuit time makes LE work properly?
Thanks.

https://www.analog.com/media/en/technical-documentation/data-sheets/611912f.pdf

 

[D.A.(Tony)Stewart]

LE is a logic function with an analog threshold of 1V +/-0.5V tolerance.
There is no in-between function to a Set/Reset Latch.

The overcurrent outputs will not latch until the LE threshold is exceeded.

 

[yefj]

Hello ,Why we put RC circuit at the input.
Why there is a need RC circuit to rise the LE input gradually?

 

[D.A.(Tony)Stewart]

The delay LE circuit is the easiest way to ignore cap. charging surges during power-up when the load is not enabled yet.

It simply permits a way to reset the ambiguous power-up state with a delay to ignore the above which might only last < 1us.

 

[yefj]

Hello , the data sheet gave a formula for this delay which I showed in the first post .
But where in the data sheet they say by how much the LE needs to be delayed ?
Thanks .

 

[FvM]

But where in the data sheet they say by how much the LE needs to be delayed ?

Page 16.

You understand that latching action creates an electronic fuse? Circuit needs to be power-cycled to reset it. Is this your use case?

 

[D.A.(Tony)Stewart]

This is a fault detection feature, but you must decide how to deal with the fault.
You can defeat the latched-off output. with a low pulse on LE if you know the fault condition is removed or recycle power to re-try.
The graph on P17 shows the RC values to achieve >= 100 us for different Vcc values.

 

[yefj]

Hello ,Yes INC1 and INC2 compared to 400mV and flags are raised for over and under current.
LE- is needed for the comparators to act safely.
Suppose V+=5V formula from page 17 is shown below.
We need to pick R and C such that the comparators will act properly.
what is meanng of t?
Why we need t>100uS?

 

[FvM]

You previously asked

But where in the data sheet they say by how much the LE needs to be delayed ?

We show the respective datasheet place.

The LE pin should remain below 0.5V for at least 100μs after power-up in order to guarantee a valid comparator outputs.

You continue:

Why we need t>100uS?

If you don't believe manufacturer statement that it's necessary for comparator power-on reset, do you expect to get more info from the community, seriously?