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Lt spice simulation of transimpedance converter circuit

mina1

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Hi to everyone. I ask you opinion on how to deal with a simulation of a capacitance to voltage converter. Basically i have an opamp to which i connect a varing capacitance capacitor Cx( indeed i would like that its value vary in a specific range) to the inverter terminal, non the non inverter terminal i have sine-modulated voltage generator Vin. In the feedback loop i have a capacitor in parallel to a resistance that set the gain of Vout with respect to Vin.

I am interested in evaluating the increasing Vout over the list of increasing Cx but i am not sure to have it done correctily.
Indeed i have set a transiet analys finishing after 10 ms and .step dec param Cx 0.2n 0.4n 0.2.

What i obtain is a colum of time step and a column of voltages that however are also negative.

Could you please provide your opinion?
 

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