Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Lowest possible PCB plane separation / maximize capacitance?

Status
Not open for further replies.

JohnG300c

Advanced Member level 4
Full Member level 1
Joined
Dec 5, 2006
Messages
117
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
2,228
I'm designing a four layer PCB and i would like to know what the lowest separation distance between the power and ground planes can be? Since the capacitance is 225 * er / t (where t is the dielectric thickness, and er = 4 for FR4) it seems like i should keep the plane separation between 3-5 mils. What is possible and a good economic choice?

I understand that there are specialty materials (ZBC) that can be used to separate the planes. Altium Designer has chosen prepreg distance of 13 mils but at that separation i only get 75 pF/sqin whereas at 3 mil i get over 200 pF/sqin.

Any general rules?
 

I have decided to upgrade to a six-layer PCB. The cost is 25% higher but i can control both the signal layer impedance as well as minimize the layer separation between the VCC/GND layers. The minimum layer separation seems to be 4 mil, with the extra layer pair i effectively double the plane area which is a great boon to EMI and ripple minimation.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top