Your power dissipation depends only on drain current and
voltage. You can throttle a high-VT device to lower DC
current than a low-VT device. But neither, in any amplifier
that's trying to run that fast, will be at so low a current
density. Only static CMOS logic. And even there, in the
core / pipeline, very little sits still.
I have worked in technology with not one or two, but four
MOS VTs per species. Slow logic used the highest VT.
Even in some CMOS logic gates, when pressed for speed
I have used the "mid-VT" devices which are more akin to
a normal "low VT" in things like the internal clocked legs
of DFFs, tolerating the worse IDD in places where that
trade was worth it (400MHz, 3.3V CMOS - not an easy
play).
Low VT will give you more saturated operating range in
low voltage analog, somewhat. High VT might let you use
larger, better matching devices at low currents and low
frequencies (like your bias racks, if bias current is low).
You might choose to begin with standard (high) VT in
everything, and substitute low-VT where you run into
speed or headroom problems, reactively. I wouldn't try
to predict point-by-point, which to use ahead of any
analysis except for things where you know that either
max speed or min current is the overarching value. In
a mix, probably best to just pick a default and deal with
the exceptions as they are revealed.