Low-side gate driver does not propagate at high duty-cycle in buck design

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nidare

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Hello!

I'm looking at a integrated buck design that in some corner cases will have to tolerate low dropout and the duty-cycle will approach ~90%.
There is a duty-limit circuit that will limit to roughly 90% but I see that the low-side gate-driver signal dies out right before reaching this limit in some corners, while the high-side gate-driver propagates all the way to the limit.

I have tried tweaking the lower side gate-driver to be able to propagate the narrow ON-pulses at 90% but this comes with some other negative consequences.

So my question then becomes:
What are the consequences of allowing the low-side gate-driver to die out at high duty-cycle, such that it is only the high-side output being toggled on and off?
 

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Yes, it has a non-overlapping region for the gate driver that ends up swallowing narrow low-side ON-time pulses while narrow OFF-time pulses for the high-side continues to propagate.

Ideally, the non-overlapping region should be made narrower to not swallow the low-side gate driver but due to other reasons this is not that easy.

I guess the buck will start behaving asynchronous when the low-side gate signal is swallowed, and the body diode takes over for the low-side switch?
I'm trying to figure out if this is harmless or not, as I did not find a good way to tweak the gate-driver

I will look into if there is any significant efficiency degradation when the body-diode takes over.
 

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You don't clearly tell if "dying out" of low side pulses is a simple effect of implemented dead-time, or if your driver has an additional minimal pulse width that abruptly cuts the output when deceeded.

A pwm output stage generally shows a current dependant error, a deviation between nominal duty cycle and average output voltage. The error increases with relative dead-time (ratio of dead-time and pwm period). The points in modulation transfer characteristic where one transistor stops switching show as additional non-linearity. Closed loop operation of the converter may become difficult beyond these points.
 
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Without detailed schematic - hard to make any guesses - if the dying out is at the Vgs-thres you could have real trouble.

better to command the lower off and let the diode do the work id the D is < 10% and the diode heat is OK.
 
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Thanks for the input guys, sounds like it needs a bit of attention.
I see some small but funky modulation of the output voltage as the low-side gate signal oscillates in and out of the region where it gets swallowed.

You don't clearly tell if "dying out" of low side pulses is a simple effect of implemented dead-time, or if your driver has an additional minimal pulse width that abruptly cuts the output when deceeded.
Click to expand...

There is a circuit in place to abruptly clamp the duty-cycle, I think my main problem is that low-side gate is filtered by propagation delay in logic/swallowed by dead-time right before the clamping steps in, while high-side manages to propagate all the way to the clamping limit. I will see if I can sort that out.
 

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Might add a back Schottky across the bottom FET to make the difference between sync and plain rect, less?
 

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dick_freebird said:
Might add a back Schottky across the bottom FET to make the difference between sync and plain rect, less?
Click to expand...
Unfortunately not an option, reducing the dead-time interval and increasing the duty-cycle limiter threshold seems to be the way to go
 

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