Low SFDR of SHA at nyquist input

[iamxo]

I designed an SHA for 14bit 100Ms/s pipeline ADC, but at nyquist input frequency(about 50MHz), the SFDR of SHA is just 70dBc from simulation. My question is where the distortion may come from.

My SHA in sample mode has an SFDR of 90dBc at nyquist input, so I think the distortion mainly comes from the gain-boosting amplifier when it is in the hold mode. Could anyone say something that cause the distortion? Vd,sat, settling curve, GBW location?? something like that..

Thank you all...

Added after 1 hours 20 minutes:

Someone told me that I should balance the noise and distortion of my SHA opamp, but I can not find the source of distortion, how can i balance?

Could anyone explain something of the distortion of the gain-boosted opamp in the hold mode??

 

[iamxo]

please help me..thank u

 

[safwatonline]

may be the sampling switch charge injection

 

[iamxo]

may be the sampling switch charge injection

But i use bottom sampling technique, which could minimize the charge injection effect.right?
Also, my SHA has settled to the desired value for 14bit resolution, but the SFDR still remains low. i am confused.

 

[wave3x]

It is strange if your SHA really settling to your final wanted value in every sample, May be you should check if your input signal's SNR be corrupted.

may be the sampling switch charge injection

But i use bottom sampling technique, which could minimize the charge injection effect.right?
Also, my SHA has settled to the desired value for 14bit resolution, but the SFDR still remains low. i am confused.

 

[iamxo]

hi, wave3x, the input signal spectrum will be degraded through sampling, in my circuit, at 50M input , the signal has 91dB SFDR in sampling mode.

btw, does different values in settling curve where the error are all in the desired accuracy cause different SFDR?? for example, in time t1, t2, the value V(t1) V(t2) is both in the range of the required accuracy, but they are different. Hope you get me.

 

[rfsystem]

I could not fully narrow down which topology you use for the sample mode and the hold mode.

I consider that while sampling the cap ist connect between signal and virtual ground somewhere buffered.

In hold mode the cap is connected between opamp output and input.

So you have four switches and I assume that there is no overlap. So the charge is preserved.

So the voltage accross the caps should have the same SFDR of -90dBc. But depending on how you much gain the opamp have and how the common mode of the output is regulated there could be a difference between the caps voltage and the opamp ouput voltage.

Could you check the difference?

 

[iamxo]

Hi, rfsystem, what do you mean by the difference of caps voltage and opamp output voltage?? Does it mean the difference voltage on the cap when it is in sample mode and hold mode?

btw, I use flip-around architecture.
Thank you.

 

[fencl]

since there's no setting error.maybe you can descrease the input range to see if the opamp's output range linearty.or use ideal vcm for input and output. sometimes virtual gound not so realise, i guess.
Btw. since i got sfdr of s/h just like adc output, catch each hold value and do fft. what's your means of sample mode sfdr and hold mode sfdr?

I designed an SHA for 14bit 100Ms/s pipeline ADC, but at nyquist input frequency(about 50MHz), the SFDR of SHA is just 70dBc from simulation. My question is where the distortion may come from.

My SHA in sample mode has an SFDR of 90dBc at nyquist input, so I think the distortion mainly comes from the gain-boosting amplifier when it is in the hold mode. Could anyone say something that cause the distortion? Vd,sat, settling curve, GBW location?? something like that..

Thank you all...

Added after 1 hours 20 minutes:

Someone told me that I should balance the noise and distortion of my SHA opamp, but I can not find the source of distortion, how can i balance?

Could anyone explain something of the distortion of the gain-boosted opamp in the hold mode??

 

[Usman Hai]

@iamxo
Hi, did you figure out the solution? Can you please share your thoughts about this.

 

[iamxo]

@iamxo
Hi, did you figure out the solution? Can you please share your thoughts about this.

uh.. It's a long time since I post this question, so i think i may forgot something.
However, i have some suggestions for designing a sample/hold amplifier which is shown as below:

1) make sure your opamp has the required gain and GBW, and if gain-boosting is used, the GBW of gain-boosting amplifier is located at the right region(there is a rule).

2) the switch size should be small enough, including sampling switch (usually you use boot-strap switch), hold switch, bottom-plate sampling switch (especially the size of bottom-plate sampling switch, it should not be too small)

3) the clock timing for sample/hold is also critical

As long as these 3 steps are followed, i think the s/h amplifier performance will not be bad. At last, my problem may come from the small size (large res) of bottom-plate sampling switch.

Hope it helps, Usman Hai, thanks for your attention.

 

[techjie]

hi iamxo
I'm confused by the same problem,you've given three suggestions.I have some question about the first one.you said

1) make sure your opamp has the required gain and GBW, and if gain-boosting is used, the GBW of gain-boosting amplifier is located at the right region(there is a rule).

where is the right region?

UGB_GB≥ UGB_MAIN_OP
is that right??or anyother position?
practically,the pole/zreo of the op with gain-boost is so complexed, it often located as a pair of conjugate pole/zeros.
how to optimize?

best regards!
holp your apply!!