urimi
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Hi,
how to reduce the power dissipation in flip flop in cmos, i saw so many papers for reducing the power dissipation. in those papers they used dual edge triggered, pulse triggered, clock swing,multi threshold, clock gating master-slave latches and conditional discharge.
i want to know the which one is the best procedure for reducing the power dissipation in flip flops. this is very important to me. it is related to my project.
and also i want to know the below topics
->dynamic vs static ff
->contional vs non conditional ff
->squarewave vs pulsed ff
Thank u in advance
how to reduce the power dissipation in flip flop in cmos, i saw so many papers for reducing the power dissipation. in those papers they used dual edge triggered, pulse triggered, clock swing,multi threshold, clock gating master-slave latches and conditional discharge.
i want to know the which one is the best procedure for reducing the power dissipation in flip flops. this is very important to me. it is related to my project.
and also i want to know the below topics
->dynamic vs static ff
->contional vs non conditional ff
->squarewave vs pulsed ff
Thank u in advance