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during the scan shift, all clockl tree run, all flop are active, the combination logic behinds also. so excepted the memories elements, the complete logic togelling, so consume!!
You need to considered the scan shift as the highest power consumer case.
Some techniques involves in the patter generated, the manner to reduce the number of toggling value. As far I know, the scan low power technique is mainly control by the DFT insertion or/and ATPG tool.
From a simulation point of view, you will notice that simulating the scan test vectors with timing takes a very long time. The reason being is that the number of scheduled events during shifting is very high; one could say worst case from a power perspective.
Theses long run-times are why scan vectors come in serial (real) and parallel test sets. The parallel sets "magically" load and unload all of the flops without shifting the scan chain; these set are good for simulating the capture cycles.
The serial sets are applied to the DUT at the tester; at a minimum, some of these vectors should be simulated to verify the complete scan test sequence for all PTVs.
For simulation , serial test sets are required, but there is always tradeoff between number of test patterns and test coverage. I'm still not sure how DFT or ATPG tools work for low power , could anybody elaborate more?
Refer Low Power fill (Synopsys tetramax)......Tetramax can generate patterns in a manner , where there is less switching between consecutive bits in a pattern.
TetraMAX fill the "unused" bits of a shift in sequence with 1s or 0s, depending on the values on the USED bits. That is, some bits of a pattern are required to be 1 or 0. Other bits are don't-cares. Usually don't cares are randomly filled. But with low power fill option (command given below) Tetramax can intelligently fill the unused bits
The "set atpg -fill adjacent" command generates patterns that switch less when shifting in.
This option can be useful to minimize power usage during scan shifting by reducing signal switching.
---------- Post added at 06:42 ---------- Previous post was at 06:30 ----------
Synopsys Solvnet article on Low Power Patterns during ATPG (PS: Login with Solvnet account)
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