seeya
Newbie level 5
With today's increasingly large and complex digital IC and system-on-chip (SoC) designs, design power closure and circuit power integrity are starting to become one of the main engineering challenges, thereby impacting the device's total time-to-market.
The shear amount of power consumed by some devices can cause significant design problems. For example, a recently announced CPU consumes 100 amps at 1.3 volts, which equates to 130 Watts! This class of device requires expensive packaging and heat sinks. The heat gradient across the chip can cause mechanical stress leading to early breakdown, and the act of physically delivering all of this power into the chip is non-trivial. Thus, even in the case of devices intended for use in non-portable equipment where ample power is readily available, power-aware designs can offer competitive advantages with respect to such considerations as the size and cost of the power supply and cooling systems.
The majority of power considerations are exacerbated in the case of low-power designs. The increasing use of battery-powered portable (often wireless) electronic systems is driving the demand for IC and SoC devices that consume the smallest possible amounts of power.
Whenever the industry moves from one technology node to another, existing power constraints are tightened and new constraints emerge. Power-related constraints are now being imposed throughout the entire design flow in order to maximize the performance and reliability of devices. In the case of today's extremely large and complex designs, implementing a reliable power network and minimizing power dissipation have become major challenges for design teams.
Creating optimal low-power designs involves making tradeoffs such as timing-versus-power and area-versus-power at different stages of the design flow. Successful power-sensitive designs require engineers to have the ability to accurately and efficiently perform these tradeoffs. In order to achieve this, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with — and applied throughout — the entire RTL-to-GDSII flow.
Furthermore, in order to handle the complex interrelationships between diverse effects, it is necessary to use an integrated design environment in which all of the power tools are fully integrated with each other, and also with other analysis and implementation engines in the flow. For example, in order to fully account for the impact of voltage drop effects, it is important to have an environment that can derate for timing — on a cell-by-cell basis — based on actual voltage drops.
The timing analysis engine should then make use of this derated timing data to identify potential changes to the critical paths. In turn, the optimization engine should make appropriate modifications to address potential setup or hold problems that appear as a result of the timing changes.
This paper first describes the most significant power dissipation and distribution considerations. The requirements for a true low-power design environment that addresses these power considerations throughout the entire RTL-to-GDSII design flow are then introduced.
Please ref: h**p://www.eedesign.com/story/OEG20030609S0059
The shear amount of power consumed by some devices can cause significant design problems. For example, a recently announced CPU consumes 100 amps at 1.3 volts, which equates to 130 Watts! This class of device requires expensive packaging and heat sinks. The heat gradient across the chip can cause mechanical stress leading to early breakdown, and the act of physically delivering all of this power into the chip is non-trivial. Thus, even in the case of devices intended for use in non-portable equipment where ample power is readily available, power-aware designs can offer competitive advantages with respect to such considerations as the size and cost of the power supply and cooling systems.
The majority of power considerations are exacerbated in the case of low-power designs. The increasing use of battery-powered portable (often wireless) electronic systems is driving the demand for IC and SoC devices that consume the smallest possible amounts of power.
Whenever the industry moves from one technology node to another, existing power constraints are tightened and new constraints emerge. Power-related constraints are now being imposed throughout the entire design flow in order to maximize the performance and reliability of devices. In the case of today's extremely large and complex designs, implementing a reliable power network and minimizing power dissipation have become major challenges for design teams.
Creating optimal low-power designs involves making tradeoffs such as timing-versus-power and area-versus-power at different stages of the design flow. Successful power-sensitive designs require engineers to have the ability to accurately and efficiently perform these tradeoffs. In order to achieve this, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with — and applied throughout — the entire RTL-to-GDSII flow.
Furthermore, in order to handle the complex interrelationships between diverse effects, it is necessary to use an integrated design environment in which all of the power tools are fully integrated with each other, and also with other analysis and implementation engines in the flow. For example, in order to fully account for the impact of voltage drop effects, it is important to have an environment that can derate for timing — on a cell-by-cell basis — based on actual voltage drops.
The timing analysis engine should then make use of this derated timing data to identify potential changes to the critical paths. In turn, the optimization engine should make appropriate modifications to address potential setup or hold problems that appear as a result of the timing changes.
This paper first describes the most significant power dissipation and distribution considerations. The requirements for a true low-power design environment that addresses these power considerations throughout the entire RTL-to-GDSII design flow are then introduced.
Please ref: h**p://www.eedesign.com/story/OEG20030609S0059