Hi, to the best of my knowledge SAR achitecture seems to be a good potential for low power application because of the low number of components and hence a low power consumption. I could find several papers to support that argument in literature. However, I am curious as to whether a dual-slope integrating ADC serves a good candidate for low power consumption, assuming speed is not the main issue. I have yet to find a low power rated dual-slope ADC in literature. Am I mistaken? Thanks
Hi,
If speed is not the main issue, you can think about sigma-delta ADCs. These converters can be very accurate while consuming low mount of power. Typically, you can reach 14-bit resolution with power consumtion less than 8mW.
Regards,
Tata
I think dual slope takes some power in the high speed logic (counter). SAR should be better. Delta sigma is too complicated and the switch cap ones are not so low power, and Continuous time are out of question for higher resolutions.
Actually, I believe the power consumption is related to the C, sampling capacitor or resoluation of the ADC. So ideally speaking, for the same resolution and same speed, the power should be the same. That means there is no compatiable to same which type is more power save. Just diff one uses for diff application
It is really not an easy answer: it really depends on the ADC accuracy (not resolution!), output data rate and cost effectiveness. For high accuracy (over 16-bit) low speed sensor application ADCs, I will favour sigma-delta ADC. But if it is only 10~12 bit range, then SAR ADC has a better chance.
Keep in mind that sensor application may require ADC accuracy (or dynamic range) from 12~18 bit! So it should be decided case by case.