pseudockb
Member level 5
Hi, to the best of my knowledge SAR achitecture seems to be a good potential for low power application because of the low number of components and hence a low power consumption. I could find several papers to support that argument in literature. However, I am curious as to whether a dual-slope integrating ADC serves a good candidate for low power consumption, assuming speed is not the main issue. I have yet to find a low power rated dual-slope ADC in literature. Am I mistaken? Thanks