Jing
Junior Member level 1
low pass filter with differential input
I designed a low pass filter. It has a PMOS bias at the top, a PMOS input differential pair and a NMOS current mirror as an active load. Then connect the output to the negative input form a unity negative feedback. Finally a capacitor is connected to the output. Simulation results show that the output dc average has 10mV difference from input dc average.
I also designed an NMOS input differential pair version of low pass filter, simulation results show that the dc offset is almost 0V, but the meausurement results show that the dc offset is at least 10mV. So this means the transistor models in the simulations is quite ideal.
Then what confused me is why the PMOS differential pair version of filter has 10mV dc offset in the simulations. If I do not connect the capacitor, it become a voltage follower. The output of this voltage follower has only 2mV dc offset compared to the input signal. But when i connect the capacitor, the dc offset become 10mV. I don't know why? My design of the PMOS differential pair version of filter has problems?
circuit diagram is attached. In fact, what I want is to get the dc average voltage of the input signal. For the PMOS input pair version, the dc operating point at the output node shows only 2mV difference from the input dc voltage. but the transcient response gives 10mV difference between the output dc voltage and the input dc voltage. For the NMOS input pair version, the dc simulation gives the similar dc operating point as the transcient response. So what is the problem of the PMOS input pair version? is it my design problem? or the cadence problem? or the model file problems?
Anyone can give me some suggestions? many thanks.
I designed a low pass filter. It has a PMOS bias at the top, a PMOS input differential pair and a NMOS current mirror as an active load. Then connect the output to the negative input form a unity negative feedback. Finally a capacitor is connected to the output. Simulation results show that the output dc average has 10mV difference from input dc average.
I also designed an NMOS input differential pair version of low pass filter, simulation results show that the dc offset is almost 0V, but the meausurement results show that the dc offset is at least 10mV. So this means the transistor models in the simulations is quite ideal.
Then what confused me is why the PMOS differential pair version of filter has 10mV dc offset in the simulations. If I do not connect the capacitor, it become a voltage follower. The output of this voltage follower has only 2mV dc offset compared to the input signal. But when i connect the capacitor, the dc offset become 10mV. I don't know why? My design of the PMOS differential pair version of filter has problems?
circuit diagram is attached. In fact, what I want is to get the dc average voltage of the input signal. For the PMOS input pair version, the dc operating point at the output node shows only 2mV difference from the input dc voltage. but the transcient response gives 10mV difference between the output dc voltage and the input dc voltage. For the NMOS input pair version, the dc simulation gives the similar dc operating point as the transcient response. So what is the problem of the PMOS input pair version? is it my design problem? or the cadence problem? or the model file problems?
Anyone can give me some suggestions? many thanks.
