low pass filter configuration in PLL?

[jordan76]

Hi

From books I saw the following low pass filter configuration (A) in PLL:
IN----R--------OUT IN-----R--------OUT
| |
C R
| |
R C
| |
GND GND

(A) (B)

What is the difference between (A) and (B)? Any comments/hints?
Thanks in advance!

regards,
jordan76

 

[Fom]

I looked at your post 5 minutes trying understand that. But I couldn't.
Sorry.

 

[huanchou]

If you use the mos cap. you should let the cap(NMOS CAP) under the resistor then tie to ground.

 

[jordan76]

Really sorry for the confusion due to the format problem!
Actually it is like the following(the arrow > only for format purpose):

IN----R1-------OUT
>>>>>>> |
>>>>>>> C
>>>>>>> |
>>>>>>> R2
>>>>>>> |
>>>>>>>GND

(A)

IN----R1-------OUT
>>>>>>> |
>>>>>>>R2
>>>>>>> |
>>>>>>> C
>>>>>>> |
>>>>>>>GND

(B)

where IN is the output from the frequency phase detector, OUT is the low pass filter output.
What is the difference between (A) and (B)? Any comments/hints?

regards,
jordan76

 

[flatulent]

The main difference is the parasitic capacitance from each node to ground and their affect on the performance. If this is inside an IC these capacitances can be very large. In discrete designs they are small.

 

[jordan76]

Hi flatulent,

Thanks for your reply!

It is inside the IC. From the perspective of transfer function, both configurations are the same. What is the effect of the different configuration on performance?
Which is preferred in practical circuit?

regards,
jordan76