Low jitter differential to single-ended converter

Status
Not open for further replies.
K

kepler_

Newbie
Joined
Sep 28, 2013
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,300
Hi everybody,

I would like to design a differential to single-ended converter for low jitter (around 100fs @100MHz in a commercial 180nm process). I have checked this topology:



Which topology do you consider to be more suitable to achieve this requeriment reducing power consumption?

Thanks a lot!

Pete.
 

That's a very simple, slow / low bandwidth comparator
and I think you need to consider things like how much
of your jitter budget is allocated to incoming noise,
supply noise etc. and how much to the intrinsic noise
of the comparator.

Low front end gain means more translation of input
voltage noise to output time noise (jitter) across the
trannsfer function slope. Your common mode and
power supply rejection would be improved by more
differential gain up front, you also want this to be
high bandwidth I presume.

You want speed and power consumption to both be
perfect? Good luck.

Insisting that jitter be < 1% of period says to me that
you're not taking error budgeting seriously - or else
somebody else has already eaten all of it.
 

Thanks a lot for your comment!

Could you suggest a topology that could improve the front end gain, please?

Regards,

Pete.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…