AKarnitski
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Is anybody know any efficient solution for 500MHz low jitter clock (<0.5ps) generation with duty cycle value of 0.50+-0.01.
Now i want to do PLL for 2GHz output from 25MHz reference and divide by 4 VCO frequency with using duty cycle correction scheme. But i think i cant get so low RMS jitter value on span 100kHz - 100MHz.
Maybe anyone know better solution for this requirements? Thanks!
Now i want to do PLL for 2GHz output from 25MHz reference and divide by 4 VCO frequency with using duty cycle correction scheme. But i think i cant get so low RMS jitter value on span 100kHz - 100MHz.
Maybe anyone know better solution for this requirements? Thanks!