Low input offset voltage op-amp!

[rficdesigner]

Dear all,

My targeted op-amp designed in CMOS has input offset voltage ~ 100 uV.

I am looking for some techniques for minimizing the input offset voltage of the op-amp.

If you have any idea please share.

Thanks and have nice time!

 

[rajanarender_suram]

find the attached paper for reference, u will be able to acheive 100uV offset with this architechture

 

[rficdesigner]

Thank you, rajanarender_suram!

 

[kwkam]

the paper only talk about the systemic offset, at the level of 100uV. The random offset will kill you. The only way to attack this problem is using bipolar input stage or trimming.

 

[dick_freebird]

The nominal offset being low, is nice - but figure you
will have device mismatch in the few to 10mV range
and you'll need some sort of active cancellation to
get a +/-100uV "stovepipe" distribution.

Nice paper though.

 

[edge_tv]

Hi look for the paper from C. C. Enz and G. C. Temes "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization". It is good summary. Or papers from delft U. they do also a lot of this stuff

 

[rajanarender_suram]

the paper only talk about the systemic offset, at the level of 100uV. The random offset will kill you. The only way to attack this problem is using bipolar input stage or trimming.

as the area of input pair increases the random off-set also decreases, and this kind of circuit is implemented to get 50uV of off-set on silicon,, important thing in the design is the tail-current impedence of the input-pair is high and the input pair area has to be large even though they work in sub-threshold region