You have to divide by 208 = 16*13, so I'd do it using a series of 4 ripple clock dividers (toggle flipflop with each output used as the clock input of the next stage).
Then the final /13 stage can be done using a regular counter. Use a MAXSKEW constraint of about half a nanosecond on the clock nets of this counter to make sure it is routed correctly even if it doesn't use dedicated low-skew clock buffers.
The final output (240KHz clock) needs to be sent to a BUFG low-skew buffer to feed the rest of your design.
You can also opt to do three /2 divisions, the /13 and then a final /2 to make the resulting clock have 50% duty cycle. Or make a /26 counter of course...
As the phase relationship between the input and divided clocks are not important, a ripple clock divider is the most economical and easy way to divide.
**broken link removed**