Low frequency Clock Question

What's better in Xilinx FPGA Design

  • External Clock circuit oscillator

    Votes: 0 0.0%
  • Internal Divider clock circuit

    Votes: 0 0.0%
  • Other Solutions

    Votes: 0 0.0%

  • Total voters
    0
Status
Not open for further replies.

OvErFlO

Full Member level 3
Joined
Dec 7, 2001
Messages
178
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,298
Activity points
1,342
A Question,
I work with Xilinx Spartan II with a 50 Mhz external Clock ,in my internal circuit I need a clock of 240Khz.
Is it better create a external circuit Oscillator or a internal Clock divider ? and How can I project this solution ?

Other Solution ??? With some Counters ???


Thanks
 

One important thing to consider is if the circuitry run by the slower clock does things that have to be time synchronized with the things run by the faster clock.
 

All circuit works with a 240Khz Clock.
 

These two frequencies are not integer related so if you need exactly 240 a counter will not work. If something near 240 is acceptable, then the internal counter would be cheaper than an external oscillator. If phase jitter is not important and you need 240 average, you could count down by 280 two times and then 281 once and then go back to 280.
 

Use a DLL, multiply by 3 and then divide by 625. I'm assuming your 50MHz is 50,000,000 Hz, not 50x1024*1024 Hz

Git
 

The DLL in Spartan II is not as powerful as that in Spartan 3 or Virtex II.
It cannot generate 240K from 50MHz. So I think you can use internal
counter, if the constraint on the precision is not very tight.
 

You have to divide by 208 = 16*13, so I'd do it using a series of 4 ripple clock dividers (toggle flipflop with each output used as the clock input of the next stage).

Then the final /13 stage can be done using a regular counter. Use a MAXSKEW constraint of about half a nanosecond on the clock nets of this counter to make sure it is routed correctly even if it doesn't use dedicated low-skew clock buffers.
The final output (240KHz clock) needs to be sent to a BUFG low-skew buffer to feed the rest of your design.

You can also opt to do three /2 divisions, the /13 and then a final /2 to make the resulting clock have 50% duty cycle. Or make a /26 counter of course...

As the phase relationship between the input and divided clocks are not important, a ripple clock divider is the most economical and easy way to divide.

**broken link removed**
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…