loop gain of hysteretic buck regulator?

I am working on a hysteretic buck regulator. I know this topology is always stable. But I have a question
about the open loop gain of this topology. Since the comparator is a non-linear circuit and I do not know
how to use linear model to represent this block. I just got a feeling that the loop gain is not very high.

Does anybody know how to calculate the loop gain of this topology? Could you provide some document?
Thank you very much!

A comparator with hysteresis simply does not have "gain," at least not in any sense that I'm aware of, at least not when it has hysteresis. I don't believe it's possible to represent if with an absolutely linear model.

I agree with mtwieg. You can't derive an equivalent time-continuous small signal model for a hysteretic controller as you can for switched mode systems with linear modulator. See:**broken link removed**

Analysis of a hysteretic controller needs to refer to non-linear control theory.

A Hysteretic buck converter is intrinsically UNSTABLE!!!!!!!!!!!

..but the instability is bounded and so you get away with it.

Any kind of Bode type control loop analysis of a hysteretic converter is entirely BOGUS.

..but the instability is bounded and so you get away with it.

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That's surely true for popular hysteretic controller implementations.

I suppose, you are able to generate an ascending oscillation with a hysteretic controller by an inappropriate control loop design, e.g. by adding poles. Also the actual dynamic behaviour, e.g. response to load steps can be expected to depend on circuit parameters. In so far I understand a demand for analysis. I imagine, that a simplified linear equivalent circuit can be made under some assumptions.

FvM is correct. A LINEAR MODEL CAN BE BUILT! The trick is what grizedale alludes to: The overall loop is an oscillator: at the switching frequency, the loop gain is unity and the phase is 360 degree. If you think about it, the oscillation cannot grow larger than rail-to-rail, as this "clipping" action reflects a loop gain reduction compared to a more "ideal" amplifier; this reduced gain via clipping sets the effective "small signal" operating point.

I recently posted an analysis of this on my blog; I give a procedure for determining the loop gain, and show that the transient response with two different feedback networks are accurately modeled (i.e. simulation with the small signal model and a full switching simulation give identical transient responses).
**broken link removed**

See: https://www.power-matters.com/Power_Matters/Blog/Entries/2012/6/8_Analyzing_Self-Oscillating_Converters.html

csawtell said:

FvM is correct. A LINEAR MODEL CAN BE BUILT! The trick is what grizedale alludes to: The overall loop is an oscillator: at the switching frequency, the loop gain is unity and the phase is 360 degree. If you think about it, the oscillation cannot grow larger than rail-to-rail, as this "clipping" action reflects a loop gain reduction compared to a more "ideal" amplifier; this reduced gain via clipping sets the effective "small signal" operating point.

I recently posted an analysis of this on my blog; I give a procedure for determining the loop gain, and show that the transient response with two different feedback networks are accurately modeled (i.e. simulation with the small signal model and a full switching simulation give identical transient responses).
**broken link removed**

See: https://www.power-matters.com/Power_Matters/Blog/Entries/2012/6/8_Analyzing_Self-Oscillating_Converters.html

Click to expand...

This is pretty interesting. I like the equivocation of comparator delay with comparator hysteresis; much easier to model that way. However, isn't the relationship between the two frequency dependent (the ramp frequency that is)? So thus isn't it dependent on the converter duty cycle? I ask because a while back I was considering using a hysteretic buck converter for a high bandwidth tracking supply, whose output would have to swing down near 0V while maintaining good transient response. While doing simulations I found that the operating frequency changed greatly as when the output dropped toward zero, which wasn't a problem in itself, but I also saw degredation in the response. After reading your paper I think it must have been due to the effective gain of the comparator changing significantly (rising, I suspect).

Also just curious, what ever became of your 20MHz buck? What application was it designed for? Were you using something fancy like GaN FETs?

caswtell, you method is very interesting way to evaluate the hysteretic converter. The whole loop is like a oscillator even though it's little bit
strange oscillator. It's not like the normal ring oscillator and it's more like a relaxation oscillator.

I agree with you that the loop gain should be exactly ONE. Since the whole system includes comparator (with hysteresis), LC filter and
feedback network. If we want to get the gain of the comparator, it's reasonable to check the attenuation gain from switch node to
feedback node. For example if the attenuation from switch node to feedback node is -40dB, the equivalent gain of the comparator should
be 40dB.

I did some experiments in my circuit, it seems that your method is correct. Thank you!

mtwieg said:

This is pretty interesting. I like the equivocation of comparator delay with comparator hysteresis; much easier to model that way. However, isn't the relationship between the two frequency dependent (the ramp frequency that is)?

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Absolutely! Under a specific set of conditions, one can substitute a delay for hysteresis in a loop like this and get equivalent results, with the delay being equivalent to the time a ramp takes to get through the hysteresis window. But change the ramp rate, and this equivalence changes. So my modeling looks at one particular operating point.

mtwieg said:

While doing simulations I found that the operating frequency changed greatly as when the output dropped toward zero, which wasn't a problem in itself, but I also saw degredation in the response.

Click to expand...

If you used a system with zero hysteresis and a fixed symmetrical delay (easiest case to analyze), you would find that the total period of the oscillation is four times that delay when you are at 50% duty cycle. This is the peak frequency, and the frequency drops to zero as one approaches zero or 100% duty cycle; the characteristic is parabolic (square law; at 25 and 75% duty cycle, frequency has dropped 25%, at 10 and 90% D the frequency has dropped about 64%). Straight hysteresis gives a similar result, and if one analyzes the loop under wide/narrow duty cycle conditions, the loop is much slower (it has to be - the switching freq has dropped appreciably.)

mtwieg said:

Also just curious, what ever became of your 20MHz buck? What application was it designed for? Were you using something fancy like GaN FETs?

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The Semtech SC220 is a standard silicon (CMOS) device; it is on the market and was originally intended for use in portables (e.g. systems operating from a single Li-Ion battery like cellphones), but optimized for three possible scenarios: those that required the smallest possible components (smallest output LC due to high freq), those where space was not at a premium and output inductor could be a small air core winding (either a coil or a PCB spiral; Semtech has a patent on a clever technique for a low EMI PCB inductor), or an application requiring exceptional transient response. see: https://www.semtech.com/power-management/switching-regulators/sc220/

csawtell said:

my modeling looks at one particular operating point.

Click to expand...

Okay, just wanted to confirm. I guess that's no different from most converter topologies. I might have to do my analysis again to see if your method of taking feedback from the switching node changes my conclusions for the hysteretic buck...

If you used a system with zero hysteresis and a fixed symmetrical delay (easiest case to analyze), you would find that the total period of the oscillation is four times that delay when you are at 50% duty cycle. This is the peak frequency, and the frequency drops to zero as one approaches zero or 100% duty cycle; the characteristic is parabolic (square law; at 25 and 75% duty cycle, frequency has dropped 25%, at 10 and 90% D the frequency has dropped about 64%). Straight hysteresis gives a similar result, and if one analyzes the loop under wide/narrow duty cycle conditions, the loop is much slower (it has to be - the switching freq has dropped appreciably.)

Click to expand...

In your experience, what is the bandwidth limitation on hysteretic converters with a given switching frequency? With standard current/voltage mode buck converters, I'm usually able to push crossover frequency of to 25% of switching frequency. Is such yield possible with a hysteretic converter?

The Semtech SC220 is a standard silicon (CMOS) device; it is on the market and was originally intended for use in portables (e.g. systems operating from a single Li-Ion battery like cellphones), but optimized for three possible scenarios: those that required the smallest possible components (smallest output LC due to high freq), those where space was not at a premium and output inductor could be a small air core winding (either a coil or a PCB spiral; Semtech has a patent on a clever technique for a low EMI PCB inductor), or an application requiring exceptional transient response. see: https://www.semtech.com/power-management/switching-regulators/sc220/

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Ah they use butterfly coils for the inductor. But is that really more space efficient than a chip inductor?

mtwieg said:

In your experience, what is the bandwidth limitation on hysteretic converters with a given switching frequency? With standard current/voltage mode buck converters, I'm usually able to push crossover frequency of to 25% of switching frequency. Is such yield possible with a hysteretic converter?

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My dc:dc designs have used feedback from both the switch node and the output. If you look at the complete loop, the unity gain crossing is 100% of the switching frequency - that's why it oscillates. But if you analyze just the outer loop around the output node (as if the inner loop from the switch node were part of the modulator itself), then the unity gain point is rather lower. The less feedback one takes from the switch node, the higher the outer loop bandwidth. Some switching audio amps have used this approach to get loop gain all the way up to the switching frequency by taking all feedback at the output (load); and rather than having to control phase at the unity gain crossing to keep the system stable, you have to provide enough phase lag to guarantee it will oscillate, so things actually get easier!

mtwieg said:

Ah they use butterfly coils for the inductor. But is that really more space efficient than a chip inductor?

Click to expand...

"Butterfly coils"? I like that description. No it takes more board space than a ferrite core inductor, but it has no "component cost". PCB area does have a cost, though. So one can optimize an application for lower cost or smaller size.

csawtell said:

My dc:dc designs have used feedback from both the switch node and the output. If you look at the complete loop, the unity gain crossing is 100% of the switching frequency - that's why it oscillates. But if you analyze just the outer loop around the output node (as if the inner loop from the switch node were part of the modulator itself), then the unity gain point is rather lower. The less feedback one takes from the switch node, the higher the outer loop bandwidth. Some switching audio amps have used this approach to get loop gain all the way up to the switching frequency by taking all feedback at the output (load); and rather than having to control phase at the unity gain crossing to keep the system stable, you have to provide enough phase lag to guarantee it will oscillate, so things actually get easier!

Click to expand...

I don't think it would be feasible for the bandwidth of the converter to extend up to the switching frequency (besides of course the bandwidth which allows the converter to oscillate). At some point I assume the comparator will act like a mixer between the ramp and the reference/error signal. For example a small signal at the reference with frequency equal to the switching frequency will have the exact same effect as a DC offset (since the comparator is effectively samples the reference). I'm not 100% sure, but I assume that at 50% of the switching frequency you'll start seeing these effects severely.

"Butterfly coils"? I like that description. No it takes more board space than a ferrite core inductor, but it has no "component cost". PCB area does have a cost, though. So one can optimize an application for lower cost or smaller size.

Click to expand...

That's what we call them in MRI. They are used to create/detect B fields parallel to the coil's surface, and have the added benefit of being resistant to interference from ambient fields.

At some point I assume the comparator will act like a mixer between the ramp and the reference/error signal. For example a small signal at the reference with frequency equal to the switching frequency will have the exact same effect as a DC offset (since the comparator is effectively samples the reference).

Click to expand...

Injecting noise at the switching frequency will indeed get aliased to DC, but that doesn't mean it's unstable, nor does it mean the switching frequency isn't included in the bandwidth. Anything around the switching frequency will get downconverted to baseband, and anything around baseband will get upconverted to the switching frequency... it's typical of any ripple regulator to be more noise-sensitive than other control schemes, although other schemes also exhibit mixing (they just happen to attenuate any high frequency noise on the output voltage before feeding them to the comparator).

An interesting corollary is that any noise that occurs at the switching frequency, such as parasitic ringing of the switch node, can cause a DC shift (or other effects, such as switching frequency jitter due to decreased ramp slope at the peaks/troughs of the ringing). Thankfully, DC shift can be servo'd out, as the 20MHz switcher's block diagram shows.

The less feedback one takes from the switch node, the higher the outer loop bandwidth.

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For maximum bandwidth (and thus, minimum closed-loop output impedance), it's best to generate a ramp from the output capacitor's ESR, rather than generating a ramp using an R-C from the switch node. The 20MHz buck was designed with the assumption that the output capacitor would be ceramic, and therefore have no ESR—so the ramp would need to be artificially generated and then injected into the control loop (some would call it a "virtual ESR," although more accurately it reflects the voltage on the DCR of the inductor). The way the voltage ramp is generated, it straddles the average switch node voltage (which isn't equal to the output voltage due to the inductor's DCR). At low frequencies the output voltage feedback dominates, and at high frequencies the ramp (switch node feedback) dominates. For maximum bandwidth, you want this handover to be at as high a frequency as possible.

If the voltage ramp straddled the output voltage rather than the averaged switch node, then there would be no need for the handover; the feedback would be perfect and the bandwidth would include the switching frequency. If you were using a ceramic output cap, this would involve introducing a physical resistor in series with it and tapping Vout from the top of the resistor (instead of from the top of the capacitor). This would introduce more output voltage ripple at the switching frequency, but the transient response to loads would be blazing fast (not that the 20MHz switcher isn't already blazing fast; it'd be even more blazing).

A side note on the "patented X-EMI inductor technology", see patent application US2006214760. Curiously, the patent has it's first 10 claims cancelled. My personal opinion is that the 11. claim describing the said butterfly coil configuration is completey prior art and won't stand a serious action of voidance...

FvM - Re patent: You are absolutely correct that claim 11 didn't pass muster - it was rejected as solidly as several rounds of previous claims. Only thing that is important is the claims that were allowed in the granted patent (US patent 7,221,251, granted May 22,2007) which limited the scope of the invention to the "method" of using these PCB spiral structures for use in switching power conversion; a far cry from granting a patent on the structure itself.

Why look up the patent application rather than the granted patent?

Why look up the patent application rather than the granted patent?

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For some reason, the espacenet browser showed the claims of the application document (A1) instead of the final (B2) document.

Fortunately I don't need to judge about the substance of final document's claims.