Ebrahim Songhori
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Hi,
I got the Loop exceeded maximum iteration limit. (ELAB-900) error in synopsys design vision. I am aware that it is not a proper usage of for in verilog. I am trying to generate a large combinational logic, that's way I need to use for loop in always@(*) statement.
I was wondering if there is a way to increase the maximum iteration limit in design vision. Right now, it is 1024 iterations per core.
Thanks,
Ebrahim
ps. I can use nested for loop to avoid this error. Apparently this approach increases the complexity of circuit, so I'd like to increase the iteration limit instead.
I got the Loop exceeded maximum iteration limit. (ELAB-900) error in synopsys design vision. I am aware that it is not a proper usage of for in verilog. I am trying to generate a large combinational logic, that's way I need to use for loop in always@(*) statement.
I was wondering if there is a way to increase the maximum iteration limit in design vision. Right now, it is 1024 iterations per core.
Thanks,
Ebrahim
ps. I can use nested for loop to avoid this error. Apparently this approach increases the complexity of circuit, so I'd like to increase the iteration limit instead.