jtag verilog
Hi,
I am trying to build my own usb to jtag converter. I have the board all designed but i'm looking for some help in getting the state machine started for the jtag communications part.
Basically, I am using a USB chip that has an 8-bit parallel bus for the data and a few IOs that I can use to trigger the state machine on the CPLD.
I am looking for some code with a state machine in verilog to send standard JTAG commands and data ( and reading back).
Any help would be appreciated!