ashishjindal76
Member level 4
SDRAM Controller
Hi
Does anybody around here has complete working code for sdram controller in verilog which is in synthesisable. the code which i have is ok but gives the problem when applied the constraints in VirtexII FPGA.
thanks
Ashish
Hi
Does anybody around here has complete working code for sdram controller in verilog which is in synthesisable. the code which i have is ok but gives the problem when applied the constraints in VirtexII FPGA.
thanks
Ashish