Looking for papers about power management in SoC

[airace]

power management:Req

Can someone post up some good info on Power management in SoCs

Thanks in adv,

 

[okguy]

A basic rules for any analog design is to have a power down mode for ALL cells. At least it save some DC power.

OkGuy?

 

[sunjimmy]

Change the sytem clock frequency during
power-down mode & aggressive gated-clock design isn't a bad idea.

Hope it helps