Re: Help for a PAL
This is probably because the signals are registered. PALxxRxx, the 'R' meen that the device have registers (flip-flop) at output. For example:
O1:= DRIN14
O2:= O1
O3:= DRIN15
O4:= O3
After CLK is given a raising edge, O1 will equal what was at DRIN14. O2 will equal what was PREVIOUSLY in O1 (so, the old O1 get shifted into O2, and O1 is now what was at DRIN14). Similar for O3 and O4.
An equivalent in verilog would be
Code:
always@(posedge CLK)
begin
O1 <= DRIN14;
O2 <= O1;
O3 <= DRIN15;
O4 <= O3;
end
Note that the / meen that output that you see at the pin is inverted. Similar for input. So, you can have a negative-asserted inut or output, but work with equations using positive-logic. This can save gates, and make the equations simpler.
So, O1 * /O2 + /O1 * O2 really give something that is not always 0. In this case, if you have, at DRIN14, a 1 at a CLK cycle, followed by a 0 at the next CLK cycle, or vice-versa, then, this will make O1 * /O2 + /O1 * O2 equal '1'. Else, if you have 2 consecutive 0 or two consecutive 1, at DRIN14, O1 * /O2 + /O1 * O2 will evaluate to 0. The result will then propagate to SETCHANGE and ININT at the next CLK raising edge.