Looking for PAL16R8 equations

[BGA]

Help for a PAL

I'm looking the eqautions of a PAL16R8 used in an old project. I need help because I never used pal.
The equations are:

Pins 1 TO 10:

CLK ENININT DRIN15 DRIN14 CHANGE0 CHANGE1 PULLUP NC NC GND

Pins 11 TO 20:

OE /O1 /O2 /O3 /O4 /SETCHANGE NC /O7 /ININT VCC

Equations:

O1:= DRIN14 O2:= O1 O3:= DRIN15 O4:= O3

SETCHANGE:=O1 * /O2 + /O1 * O2 + O3 * /O4 + O4 * /O3 +
+ CHANGE0 + CHANGE1 + /PULLUP

O7:= ENININT

ININT:= O7 * (O1 * /O2 + O2 * /O1 +O3 * /O4 + O4 * /O3 +
+ CHANGE0 + CHANGE1 + /PULLUP)

Looking the equations it seems that:

the output /SETCHANGE it's the negate of (CHANGE0 OR CHANGE1 OR PULLUP)

and the output /ININT it's the negate of ENININT AND (CHANGE0 OR CHANGE1 OR PULLUP).

Is it correct ?

If yes, why the designer uses in the equations the signals O1 * /O2 + O2 * /O1 etc. etc. that results in a logic 1 ever (O1 and O2 are ugual).

Thanks in advance.

 

[eltonjohn]

Re: Help for a PAL

No .. I don't understand when you say the :
the output /SETCHANGE it's the negate of (CHANGE0 OR CHANGE1 OR PULLUP) .. what do you do with the other terms . If you use demorgan's theorem it won't simplify to what you say it's a much more complicated equation .
and the expression may contain more than 8 Pterms .. So with PALS and in general with programable logic . You have the option to invert the output .So is better sometimes to choose the equation that contains fewer terms and later invert it on the output pin ,Otherwise it may not fit inside the PAL architecture .. or waist resources and power!

you can do this /A = equation when you are shure that this is going to simplify to fewer terms ..
In any case is very simple to test if it simplifies to what you said

Do this

declare
Pins 11 TO 20:

OE /O1 /O2 /O3 /O4 SETCHANGE NC /O7 ININT VCC
( no bars here)

/ININT:= O7 * (O1 * /O2 + O2 * /O1 +O3 * /O4 + O4 * /O3 +
+ CHANGE0 + CHANGE1 + /PULLUP)

/SETCHANGE:=O1 * /O2 + /O1 * O2 + O3 * /O4 + O4 * /O3 +
+ CHANGE0 + CHANGE1 + /PULLUP
(bars here)

product terms on a Pal are at most 8 terms (8 inputs to AND gates)
here you have 12 inputs so if you use demorgan .. you might end up with
Pterms that contain more than 8 inputs ..won't fit !
Expresso wich is the algoritm used to simplify will try to reduce these equations and if won't complain my appologies for talking too loud !
But i'm affriaif that it will .. let me know !

 

[BGA]

Re: Help for a PAL

My problem it's only to understand the function of the pal regarding the two output:
/SETCHANGE
/ININT

I don't know nothing about Pal .... I have to reproduce the function into an fpga.
The problem is that I don't understand how the two outputs depend from the inputs.

If you see:

O1=O2
O3=O4
so, O1 * /O2 ( I think it seems: O1 AND (NOT O2)... is it right?) , when O1 is equal to O2 is an expression that is ever false (0). Is it correct?

 

[eltonjohn]

Re: Help for a PAL

NO!!!!!!!!!!!!!!!!!!!
You don't have this !

O1=O2
O3=O4

what you have is THIS

O1:= DRIN14
O2:= O1
O3:= DRIN15
O4:= O3

: = REGISTERED LOGIC IMPLIES A
D FLIP FLOP

 

[Big Boy]

Re: Help for a PAL

This is probably because the signals are registered. PALxxRxx, the 'R' meen that the device have registers (flip-flop) at output. For example:

O1:= DRIN14
O2:= O1
O3:= DRIN15
O4:= O3

After CLK is given a raising edge, O1 will equal what was at DRIN14. O2 will equal what was PREVIOUSLY in O1 (so, the old O1 get shifted into O2, and O1 is now what was at DRIN14). Similar for O3 and O4.

An equivalent in verilog would be

always@(posedge CLK)
begin
   O1 <= DRIN14;
   O2 <= O1;
   O3 <= DRIN15;
   O4 <= O3;
end

Note that the / meen that output that you see at the pin is inverted. Similar for input. So, you can have a negative-asserted inut or output, but work with equations using positive-logic. This can save gates, and make the equations simpler.

So, O1 * /O2 + /O1 * O2 really give something that is not always 0. In this case, if you have, at DRIN14, a 1 at a CLK cycle, followed by a 0 at the next CLK cycle, or vice-versa, then, this will make O1 * /O2 + /O1 * O2 equal '1'. Else, if you have 2 consecutive 0 or two consecutive 1, at DRIN14, O1 * /O2 + /O1 * O2 will evaluate to 0. The result will then propagate to SETCHANGE and ININT at the next CLK raising edge.

 

[BGA]

Re: Help for a PAL

OK... now I understand.
Thanks you very much.

Excuse me.... but I don't know nothing about pal and didn't know that the signal are registered.