Looking for new HDLC controller IP core

[7rots51]

Hello

I need a HDLC controller IP c0re .I saw the one in openc0res.com,but I need new ones,it is better it be in verilog.

bye

 

[cganeshprabhu]

vhdl hdlc code

HI,

Here is a full project in HDLC. But in VHDL.

Regards,
GP

 

[etherboy]

hdlc verilog

www.opencores.org there are some things about HDLC in it

 

[kairimai]

hdlc transceiver

3q


Useless post.
Warning!

--
makswell

 

[Black Jack]

Re: HDLC-IP

HI,

Here is a full project in HDLC. But in VHDL.

Regards,
GP

It`s VERILOG
Do you have this project in VHDL?

 

[hoangde]

HDLC-IP

I'm looking for it

 

[calvinhorng]

HDLC-IP

I wonder anyone has tested the code link with commericial HDLC?

 

[shangool]

HDLC-IP

Hi,

I've done it, but i think you'd better do your job yourself unless you're going to pay for it. Anyway I am summarizing my job (Implementation of an HDLC transceiver with FPGA) in a paper. As soon as I could prepare it, I'll send it to you.

Be successful,

 

[vijayanand_ME]

Re: HDLC-IP

it is not working properly..
In Open cores hdlc code... last byte is getting repeated in the transmission that to for 7 bits ..
In the Project post.. Test bench data is woring fine.. If i transmit 0xFF, 0 xFF, 0x01, 0x00 then the result is 0xFF, 0xFF, 0x00, 0x00.
Any one have faced these problems??