Looking for methods for offset-voltage reduction

decreasing thd of an opamp

Specification:
Operating range(VCC) :8-10v
output loading: RL=10k,CL=100pF
Gain: >=70dB@VCC=9V
PSRR: 80dB@VCC=9V,power ripple=0.2Vrms,1KHz
GBW: >=8M@VCC=9V
Phase Margin: >=45 degree @VCC=9V
Vin_max: >=7.5V@VCC=9V
Vin_min: <=1.5V@VCC=9V
Output swing: 2Vrms@RL=10K,CL=100pF,THD<0.2%,VCC=9V
Quiescent Current: <=1mA@VCC=9V, no load
Max offset: <2mV
Die area: <=60000 um2
Process: 1um,9V CMOS process
The main specification is offset-voltage.This is difficult for me,because only five PADs can used(VCC,GND,INN,INP,OUT).So, I can't use auto-zero or trimming techniques.
Anyone knows other method about offset-voltage reduction?
Please help me.My email address: muldersun@hotmail.com
I'll appreciate.

Best regards,
Mulder Sun

Re: Help: About opamp design

Try to increase the input stae sizing and decrease the input stage tail current.

Re: Help: About opamp design

Another:
Please pay attention to you layout, symmetry is needed.

Help: About opamp design

but the two methods is hardly to decrease the offset to lower than 2mv, any better method?

Re: Help: About opamp design

I think auto-zero can do this job because this method don't need any external pin.
Only trimming needs more pins to share.

Re: Help: About opamp design

leo_o2 said:

I think auto-zero can do this job because this method don't need any external pin.
Only trimming needs more pins to share.

Click to expand...

But I think the die area is limited.

Help: About opamp design

the offset is mainly caused by the gain of the two input stages ,can the AGC be used here?