Looking for materials on Power-ON reset circuit

[snoop835]

Power-ON Reset

Hi all,

Can someone show me a good journal or reference on Power-On reset circuit? I plan to design one with VDD=1.8V, Trip point say 1.5V which is accurate across temperature and VDD variations.

Cheers

-snoop835-

 

[ambreesh]

Re: Power-ON Reset

hi,

I had uploaded some papers on POR.
Look in IEEE study papers

 

[snoop835]

Re: Power-ON Reset

Hi ambreesh,

Can you the papers in this forum so that I can upload it.

Cheers

-snoop835-

 

[piao]

Power-ON Reset

Just using the RC structure, charge up the capacitor, then you can get the POR circuit.

 

[bor]

Re: Power-ON Reset

hi dude, it me azrin..well i am designing the same POR too, i am using transistor that have th=0.6 and vdd at 1.2V, so any info on how to start that

 

[montage2000]

Power-ON Reset

the principle is charge a cap through large resistor , the RC constant determine the POR time

 

[snoop835]

Re: Power-ON Reset

Hi guys,

I am designing a POR circuit based on AMD patent "Precision Power-ON Reset with improve accuracy" Patent No: 6137324. This circuit is a bandgap like Power-ON reset which is different from conventional RC structure Power-ON Reset circuit. The circuit is triggered by a logic state hence to generate POR signal.

My problem is during the initial condition where the Vdd start to ramp-up from 0V to VDD (1.8V), there are so many uncertainty states in the logic circuit that cause the POR to fail. Is there any good initializer circuit which more robust to trigger my POR? Any reference from journals?

Appreciate any comments.

-snoop835-

 

[electronrancher]

Power-ON Reset

Are you sure your problem is in the logic and not in the self-biased current source? This guy, as drawn, is not guaranteed to start up. You should make your PTAT current by another means that is guaranteed to start up. Once that is working you should be fine. One other thing I see is pmos 528 might should be a resistor - otherwise, it's logic output is not valid until the self-biased stage is up so at very low input voltage you have a hole in your POR - the evil "diode glitch"!


This is a strange patent - do you guys think it is really valid? It looks to me that it is commonly known technique and is not a novel invention. Basically it is making a bandgap where the voltage across R2 is the gain of the PTAT current, and is summed with the Vbe of the npn. Now you can further multiply this "bandgap voltage" by making the R2/R3 divider, but that does not make it novel.

Does it?

Taking another look, I see that the npn must be fed by the ptat current, a simple resistor may not suffice since the collector current would then be non-ptat.