Looking for jittered clock module in verilog...?

[bulerias1]

hi,
i need to add my simulated core an input clock,with configurable jitter option...does someone know how to do it...?,or maybe have such a model...in verilog?
thanks,
bull

 

[adanshen]

a global jitter is easy to generate,
to pass that test does not ensure your success, you should generate clock difference in different parts in your module

 

[sandusty]

there are two kind of jitters... long term jitter and short term jitter... both canNOT be cought with a global clock modification

 

[always@smart]

there are two kind of jitters... long term jitter and short term jitter... both canNOT be cought with a global clock modification

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Hi sandustry,

can you be more specified that what are so-called long term and short term jitter.

How much jitter we should consider in the synthesis?

always@smart

 

[sandusty]

Hi, always@smart:

If there is a clock, for each cycly, the clock period is 0.001% longer than the expected and after 100's k cycles the period getting shorter ... it will cause some problems on the display controller..

Short term jitter is the jitter we normally defined

The jitter your need to consider depends on your application...

 

[always@smart]

sandustry,

you got "PM"