Looking for info about scripts and power estimation in Synopsys

[negreponte]

I am new In Synopsys.
Could you give me information about
scripts in synopsys
power estimation in synopsys

Thanks

 

[diemilio]

Re: synopsys question

What kind of scripts are you looking for??

Logical synthesis?
Physical synthesis?
STA?

which of all synopsys' tools are you planning to use?

 

[quan228228]

Re: synopsys question

to diemilio：
Couldy you share scripts for logic synthsis including powr optimation and dft.

and ATPG script.


Thanks!

quan2228228

my email: quan228228@hotmail.com

 

[negreponte]

Re: synopsys question

I have implement algorithms and i want to have resullts in area, power and frequency.
My system has three basic inputs A(m-1 downto 0), B(m-1 down to 0) and R(m-1 downto 0) and its operation completed after m cycles.
A, B are random but R belongs to a specific set of numbers.
I want to find which R number gives me the best results in terms of power.


Thank you

 

[diemilio]

Re: synopsys question

Well, I'm not an expert in this subject since I have been working just for 6 months all by my self (no tutors!!!). Nevertheless I'm gonna post a script I used to synthesize an up/down counter using Design Compiler and a TSMC 0.15 um library. There's no power optimization there, but you can use PrimePower or Power Compiler to do power optimization and analysis. Check out the User Manuals for those two tools.

(ignore the comments, they're in spanish)

Hope this helps,

diemilio

 

[diemilio]

Re: synopsys question

Here's another script. It belongs to Ohio State University. At the end of the script they use a couple of commands to report violations.

I hope this helps,

diemilio

 

[funzero]

Re: synopsys question

you can search google " checklist for dc synthesis "

 

[Jugantor]

Re: synopsys question

I am facing a simple problem.while trying to read a verilog file using
read_verilog -hdl_compiler filename ,

we need to enter Control-c 3 times to terminate the reading process(as mentioned in the documentation ) , but it so happens that even the primepower gets terminated.

Can u plz tell me how to terminate the reading process without terminating the primepower ?

Thanks & regards,

Jugantor

Added after 1 hours 3 minutes:

another problem..:

i have a DMA module...and have got a set of files. like Edge_fifo.v, socket.v...which are part of the project files. now for running the power analysis using primepower, i need to check out these files also ...as because the interface part is the most power hungry part of any dma controller system(we know it b4hand.)....

the problem is how can i link these subsidiary files (like edge_fifo, socket ) with the DMA file so that i can get the power numbers for the interface regions also?

plz help me..if u didnt get the problem properly....feel free to mail me at:

jug_nitd(at)yahoo.co.in
or
jug.ece(at)gmail.com
[/u]

 

[diemilio]

Re: synopsys question

Are those files (Edge_fifo.v, socket.v) synthesized??
Are you using Design Compiler to do your synthesis??

diemilio

 

[shiv_emf]

Re: synopsys question

I am facing a simple problem.while trying to read a verilog file using
read_verilog -hdl_compiler filename ,

[/u]

r u using latest version of DC??

u need nt use -hdl_compiler!

 

[Jugantor]

Re: synopsys question

HI shiv_emf,
you are correct. while using design_vision/DC, I dont need to use -hdl_compiler
. But I am using primepower actually for my power analyis. (the newest version)There I need to use -hdl_compiler .
Its bcoz if I dont use it, then the read_verilog filename.v invokes the native Primepower Verilog reader to read the file. As the reader is strictly limited to structural Verilog, any other construct results into a syntax error.using read_verilog -hdl_compiler rectifies this problem.

But as i said , whenever i use -hdl_compiler, the primepower keeps on reading and doesnt terminate.
and if i enter Cntrol+c 3 times, the whole primepower gets terminated.



Added after 29 minutes:

@diemillio

I forgot to give you the total information.
actually , all these files, eg. EdgeFIFOs, Socket_FIFO are BluespecSystem Verilog(BSV) files. They are actually EdgeFIFO.bsv & Socket_FIFO.bsv files.
As they are kind of library files used for the DMA controller system
Hence its not possible to generate their verilog files.
Hence they cant be synthesized even.
so How can I run a power analysis on the DMA to know its power hungry parts using primepower?

I have tried in Design compiler too.
these files are not getting instantiated into it

 

[diemilio]

Re: synopsys question

How are you linking those files with the top block???

Are you including them in your "link library" list??

 

[Jugantor]

Re: synopsys question

@diemillio

Thats what I need to know. How can I link those .bsv files (like Edge_FIFO , Socket_FIFO)with the actual DMA file during sythesization ,so that those files are also taken into account(which is not happening now) ?

Its because design_vision doesnt take .bsv files. and those particular .bsv files cant be converted into their Verilog equivalent files

Thanks & regards,

Jugantor

 

[diemilio]

Re: synopsys question

@diemillio

Thats what I need to know. How can I link those .bsv files (like Edge_FIFO , Socket_FIFO)with the actual DMA file during sythesization ,so that those files are also taken into account(which is not happening now) ?

Its because design_vision doesnt take .bsv files. and those particular .bsv files cant be converted into their Verilog equivalent files

Thanks & regards,

Jugantor

Well, I'm not completely sure, but I don't think Design Compiler nor PrimePower support bsv files. What I think you should do is:
take Bluespec Compiler (BSC) to compile those .bvs files into RTL Verilog files (blablabla.v).

And then include those files in your primepower link_library, obviously changing the instantiation names on your top block.

hope this helps,

diemilio