Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Just like tanner and cadance,lasi is a software to draw layout of IC's. But the environment and technology covered is for BJT/TTL technolgy. The design is different from CMOS technology.
In CMOS a transistor bild by square poligon of poly, ntype and ptype basically. Well for BJT we build emmitter, base and collector. Also in squre polygon accept for the emmitter in circle.
LASI is build for BJT environment, so all the parameters and technology used is following the spec for BJT transistors. Not suitable for CMOS, as tell by the author.
But many people do make CMOS layout using LASI. For drawing the LAyout yes u can draw it, but I'm affraid u will have problems to analyze it.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
