1. Less breakdown
2. Gate leakage
3. High mismatches
4. Less DC gain
5. Very high flicker noise
6. Gate stress induced threshold shift
7. High mask costs
The main problem is that the design issues popping up after project decision could ruin the advantages of having higher density digital.
So for Analog/Digital partioning higher than 50/50 I would avoid using actual digital CMOS for high analog content.
If the analog design part takes 50% longer because of the issues the cost advantage is easy distroyed.
In the latest JSSC, TI has published one paper of a 90nm GSM/EDGE/CDMA2X transceiver. There are also many companies working on 65nm analog/RF projects. The main benefit is the integration with digital circuits.
There is a lot of analog design in 90 and now 65... especially in SOC. There are problems but the principles are exacly the same. Anyway fabs offer high voltage devices with thicker oxide so ... it depends what you call 90nm .
Before discussing the "drawbacks" or "great features", it is necessary to know the applications intended. What is the Peak-to-peak voltage, .. Where can that voltage range is applicable. In short, Applications?!?!?!?!
For 90nm onwards foundries are providing an additional tool called Design for Manufacturing which are guidelines to improve yield. Basically for Analog circuits it means larger layout offseting the gain in scaling. But since Analog follows Digital for SOC it is still beneficial.
Mismatch is worse simply because ΔL/L is larger in smaller feature sizes. For example a 1 nm error in L would be about 10% of the length in a 90 nm design whereas it'd be absolutely negligible for a 1 um design.
Offsets increase for small areas for the same reason.
It is correct that matching improves as the thickness goes down. So for equal absolute area the matching improves indeed. But the voltage swing decrease at the same time. So the effect is that scaling of analog stops around 0.25um. Only if the analog has to strictly be within the digital it could offset the disadvantages.
From the project perspective analog design in high density digital takes longer and result in higher die cost of the analog contend. That should be carefully justified.
In my present company, we are already doing cmos layout (NOR FLASHwith ANALOG circuits in the periphery). Presently its on 65nm. So to answer orig post... it is possible...
It is true that CAPS and larger high current devices cannot be shrinked to deliver power requiremens but these devices are then fingered or divided into smaller devices to improve yield.