Looking for info about analog IC design at 90nm CMOS

[Puppet1]

Analog IC Design at 90nm

Any information about Analog IC Design for 90nm CMOS ?

Thank you.

 

[lete]

Analog IC Design at 90nm

I think we can not design analog IC with 90nm CMOS

 

[elbadry]

Re: Analog IC Design at 90nm

I think we can not design analog IC with 90nm CMOS

Yes we can. There are RF designs made on 90 nm. In JSSC, 2005 issue an LNA on 90 nm is reported...

 

[bollu]

Analog IC Design at 90nm

I think we can.however analog layout will use many times bigger than the normal feature size.

 

[dachou]

Analog IC Design at 90nm

question
how analog circuit work when gate leak ?

 

[khouly]

Re: Analog IC Design at 90nm

in analog design which the frequency is not very high , usually the transistor L is 3 times the minimum l of the technology

but if u want RF circuits operating in multi GHz , u need to use L min to get this frequency


khouly

 

[rfsystem]

Re: Analog IC Design at 90nm

Nearly everything is worse in 90nm.

1. Less breakdown
2. Gate leakage
3. High mismatches
4. Less DC gain
5. Very high flicker noise
6. Gate stress induced threshold shift
7. High mask costs

The main problem is that the design issues popping up after project decision could ruin the advantages of having higher density digital.

So for Analog/Digital partioning higher than 50/50 I would avoid using actual digital CMOS for high analog content.

If the analog design part takes 50% longer because of the issues the cost advantage is easy distroyed.

 

[dumbfrog]

Analog IC Design at 90nm

Yes, I have seen 65nm SRAM (analog sensamp, bg, etc)

 

[Puppet1]

Re: Analog IC Design at 90nm

how to get higher gain for 90nm for rf designs?

 

[sdwireless]

Analog IC Design at 90nm

In the latest JSSC, TI has published one paper of a 90nm GSM/EDGE/CDMA2X transceiver. There are also many companies working on 65nm analog/RF projects. The main benefit is the integration with digital circuits.

 

[ocarnu]

Re: Analog IC Design at 90nm

There is a lot of analog design in 90 and now 65... especially in SOC. There are problems but the principles are exacly the same. Anyway fabs offer high voltage devices with thicker oxide so ... it depends what you call 90nm .

 

[srivatsan]

Re: Analog IC Design at 90nm

Before discussing the "drawbacks" or "great features", it is necessary to know the applications intended. What is the Peak-to-peak voltage, .. Where can that voltage range is applicable. In short, Applications?!?!?!?!

Srivats

 

[ccw27]

Re: Analog IC Design at 90nm

For 90nm onwards foundries are providing an additional tool called Design for Manufacturing which are guidelines to improve yield. Basically for Analog circuits it means larger layout offseting the gain in scaling. But since Analog follows Digital for SOC it is still beneficial.

 

[extraord]

Re: Analog IC Design at 90nm

hi guys,
i don't know why the offset/mismatch of mos increase under 90nm.
since the vt mismatch seems positive with tox.

 

[elbadry]

Re: Analog IC Design at 90nm

hi guys,
i don't know why the offset/mismatch of mos increase under 90nm.
since the vt mismatch seems positive with tox.

Mismatch is worse simply because ΔL/L is larger in smaller feature sizes. For example a 1 nm error in L would be about 10% of the length in a 90 nm design whereas it'd be absolutely negligible for a 1 um design.

Offsets increase for small areas for the same reason.

 

[rfsystem]

Re: Analog IC Design at 90nm

It is correct that matching improves as the thickness goes down. So for equal absolute area the matching improves indeed. But the voltage swing decrease at the same time. So the effect is that scaling of analog stops around 0.25um. Only if the analog has to strictly be within the digital it could offset the disadvantages.

From the project perspective analog design in high density digital takes longer and result in higher die cost of the analog contend. That should be carefully justified.

 

[mask_layout]

Analog IC Design at 90nm

In my present company, we are already doing cmos layout (NOR FLASHwith ANALOG circuits in the periphery). Presently its on 65nm. So to answer orig post... it is possible...
It is true that CAPS and larger high current devices cannot be shrinked to deliver power requiremens but these devices are then fingered or divided into smaller devices to improve yield.