Mmm... DFT. Are you saying design for testing? Or something else?
In FPGA, all we use is the JTAG. I don't think people know what you want to say. Please be specific.
Sorry fo the confusion. What I want is Windows-based FPGA tools
that can not only translate RTL to FPGA cells but also insert the
scan-chain (or JTAG). We would like to verify that the JTAG (or the
scan chain) is inserted correctly and the system can work with
external developement environment.
If not Windows-based tool can do that, is there any tool on Unix
able to do so?
The term "scan chain" refers to test process used in ASIC. Basically
all the flip-flops of the ASIC are conserted to scan-flops ( A flop with
a mux on the D input). The first input of the mux is used for normal operation. The second input is used to put the FFs in deasy chain.
A test pattern is then serialized in and and a second chain is used to
serialise out and compared with the expected pattern.
What you are refering to is "boundary-scan". This test only validate
the I/O registers of a component. Basically you use the JTAG to force
data on the Outputs or Capture data on Inputs.
All the FPGA I used already have this feature built-in. All you need is
the BSDL file from the vendor and a JTAG software.
FPGA's have in-built scan-chains(Well it depens on your vendor actually).so we just cant insert any scan chain into it.They are already fabricated.To introduce scan chains you need special scan-flops.I would suggest you to read more about this from xilinx.e.g. in spartan 3e has scan-chains.
shell3 said:
All the FPGA I used already have this feature built-in. All you need is
the BSDL file from the vendor and a JTAG software.