Looking for floorplanning guidelines

[urslen]

Floorplanning Guideline

Can anybody suggest me some conceptual guidelines to floorplan.

eg.
•Why macros are preferred to be placed at corners.
• some DOs and Don'ts that is followed in industry.

not much tool-specific guideline. But which can be very useful for tapeing out a real chip.

 

[alzomor]

Re: Floorplanning Guideline

Hi

yo can check this link
few but valuable

http://www.williamson-labs.com/480_lay.htm

Salam
Hossam Alzomor

 

[aravind]

Floorplanning Guideline

Hi hossam Alzomor
whether it is related to Floorplan Issue?
before posting reply u must check the question.

Hi urslen
1.Macro r power hungry part of ur chip . and power routing is major problem for Hard macros like memory(RAM).
2. U must place blocks according to routablity and optimaztion /SDC constraint ISSUES

 

[anjali]

Re: Floorplanning Guideline

macros r placed at corners, for better routability and if they placed at corners, they will not devide the logic area so that the compleate logic can be placed with less congestion.

 

[urslen]

Re: Floorplanning Guideline

I got some outline for a starting guideline. can any body help me to make it more helpful. Somebody may touch up on the document enclosed and give their views and suggestion as per their experience.

 

[aravind]

Floorplanning Guideline

Hi Urslen
If u wanna learn more about floorplan and other PD related issues. work in silicon ensemble tool from cadence. it that tool u have to do all manual and check out.
SOC encounter really sucks beginners