Looking for detailed info about TSPC DFF

[master_picengineer]

tspc dff

Hi everybody,

Can someone provide me with the internal circuitry of a TSPC DFF. I need the internal shematic of such a dff at the transistor level to design it and simulate it using Cadence tools.

Thanks in advance.

I found in this paper a solution
**broken link removed**

Could someone explain how does it works ?
Thanks

 

[safwatonline]

tspc dff

let clk='0'
MPS1 is ON and y1=Db
MPS2 is ON and y2='1'
Qb(now)=Qb(old) ; MP2 is OFF and MNS2 is OFF

now clk='1'
MPS1 is OFF and y1=Db;
MPS2 is OFF and y1=D;
MNS2 is ON and Qb=Db;
normal +ve edge triggered DFF

notes:
1-if D changes after clk='1' then u have two cases:
i- if D:'0'>'1' then y1 will be '0' but y2 will not change i.e. Qb is not affected
ii- if D:'1'>'0' then y1 is not affected so Qb is not affected

2- if D changes during clk='0' then u have two cases:
i- if D:'0'>'1' then y1='0' , but y2 still= '1' therefore Qb is the same.
ii- if D:'1'>'0' then y1='1' , but y2 still= '1'therefore
Qb is the same.

 

[master_picengineer]

tspcdff

Hi safwatonline,
Barkallahou fik ya 5ouya le3ziz. Thank you.
Brabbi Can you tell me safwat:
1- What makes these DFF speed compared to other DFFs
2- Conventional DFF copies the input at the clock signal. Should I add an inverter to make the TSPC dff so or there is another solution. coz i need Q as output and not Qb.
Awesome thanks.

 

[rania_hassan]

tspc inverter

AA,
Back to Rabeay
Start with Chapter 7, if you find anything difficult, back to Chapters 5 & 6
best regards,
Rania

 

[stoned]

*.dff

GOOD!

BTW:The ratio of MPS2 is larger than MPS1

 

[yashiro]

tspc +dff

Hi safwatonline,
Barkallahou fik ya 5ouya le3ziz. Thank you.
Brabbi Can you tell me safwat:
1- What makes these DFF speed compared to other DFFs
2- Conventional DFF copies the input at the clock signal. Should I add an inverter to make the TSPC dff so or there is another solution. coz i need Q as output and not Qb.
Awesome thanks.

1. It sais in the article. In conventional DFFs the clock is inverted and because you dont get CK and NCK you have to invert the clock inside the DFF. That causes a dellay for the clock and that also take up additional space.
2. I dont see a problem in adding an inverter at the output

 

[master_picengineer]

tspc d ff

Hi Friends,
Please help. I need your help urgently. I Simulated the flip-flop. But I couldnt' get why at the clock falling edge (in waveforms highligthed in red) the Output voltage of the dff decreases a little bit. Please How can I resolve this problem ?

 

[yashiro]

falling edge tspc

If you need Qb just ad 2 inverters at the output.

Make sure to have the first inverter in the chain with a small Pmos. Eventually increase the L of that PMOS

 

[master_picengineer]

falling tspc dff

If you need Qb just ad 2 inverters at the output.

Make sure to have the first inverter in the chain with a small Pmos. Eventually increase the L of that PMOS

Thanks yashiro,
The data is already inverted. I thing you mean Q.
For the inverter I thing I need only one inverter. Isn't that ?
More have I to add the inverter in the input or the output of the flip flop.
Will this reduce the problem of instable output ?