Looking for a chip that does HDLC protocol

[7rots51]

Hello

Is there a chip that do the HDLC protocol? It gets the packets from the serial line and place at a Rx FIFO ,and get data from Tx FIFO and packetize it and place it on serial line.

Please give IC part number or a circuit that can co this job.

Thanks

 

[dainis]

hdlc chip

For what speed ? (xx KHz xxx KHz x MHz xx MHz)

Two fast (up to 10MHz) HDLC intefaces, and ( optional Fast Ethernet)
interface have Samsung S3C4530 and S3C45100, price 15 USD.


Also look Zilog serial controllers:
https://www.zilog.com/docs/serial/scc_family.pdf


For FPGA:
https://www.opencores.org/projects/hdlc/

 

[elcielo]

hdlc ic

Zilog - HDLC chip, MCU with HDLC
Samsung - MCU(S3C4510 - Arm7) with HDLC
Hitachi - HDLC chip
Infineon - HDLC chip, MCU(C165 UTAH, C165 H) with HDLC
Samsung - MCU(Arm7) with HDLC
AMD - MCU(Am186cc) with HDLC
Motorola - MCU(MC68302 & MPC860 & MPC8260) with HDLC
Rabbit - MCU(R3000) with HDLC
Mindspeed - HDLC chip
infinior - MCU(ims16c - x86 compatible) with HDLC www.infinior.com

Z85C30 & Z85230 - It's popular & best.

Samsung S3C4510 - It's good & cheap.

MPC8260 - It's High-performance & expensive.

 

[7rots51]

hitachi hdlc protocol

Hi

My speed is under 100KHZ (speed is low).

I have a need for HDLC impelementation,The time is critical for me.Is there a solution(a circuit with 74HCXX ICs) with logic ICs that are more available and want less time to find.

Can I implement the HDLC protocol by a C software in 8051 micros for low speed applications?how?

Thanks for your helps.

 

[elcielo]

hdlc chips

8XC152JA/JB/JC/JD
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCONTROLLER

Multi-Protocol Serial Communication I/O Port (2.048 Mbps/2.4 Mbps Max)
–SDLC/HDLC Only
–CSMA/CD and SDLC/HDLC
–User Definable Protocols

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80C152 clone

InnovASIC, Inc.
http://www.innovasic.com/pdfs/IA80C152.pdf

Kawasaki Microelectronics
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[elcielo]

hdlc microcontroller

Philips

XA-H4(HDLC, maybe 80251 upgrade version)

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SC26C562, SC68C562, SCN68562; CMOS dual universal serial communications controller (CDUSCC)

SCN2652/SCN68652; Multi-protocol communications controller (MPCC)

 

[elcielo]

interface hdlc

HDLC is hardcoding(heavy programming).

flag, NRZ or NRZI, CRC generation, zero insert, etc...

I suggest using HDLC chip or MCU with HDLC.

 

[elcielo]

80c152

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High Speed Data Link Controller(HDLC)

PartNumber Description
PT7A6525 Dual-channel Protocol Controller
PT7A6525L Dual-channel Protocol Controller
PT7A6526 Single-channel Protocol Controller
PT7A6527 Quad-channel Protocol Controller
PT7A6632 32-Channel Protocol Controller

 

[chinara]

hdlc arm7

Mindspeed also has some chips which are very powerful on HDLC.

 

[papyaki]

edaboard

Hi,

Infineon SAB82525 : h**p://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/prod_ov.jsp?oid=13611&cat_oid=-10078

* = t

 

[calvinhorng]

hitachi protocol hdlc

The ADMteck ADM6993 will do the job.
And Admtek is now Infineon.

 

[dainis]

hdlc + interface

The ADMteck ADM6993 will do the job.
And Admtek is now Infineon.

But this chip, now is out of production .....
"we were phasing out AT8993 from the end of last year"

 

[elsalvador]

sdlc interface

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DS3134
CHATEAU - Channelized T1 and E1 And Universal HDLC Controller

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DS31256
256-Channel, High-Throughput HDLC Controller

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DS31256 and DS3134 HDLC Controller Comparisons
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[elcielo]

hdlc mcu

ARM7 STR7 32-bit Microcontroller Family

http://mcu.st.com/mcu/inchtml.php?fdir=pages&fnam=str7

http://mcu.st.com/mcu/modules.php?name=mcu&file=pfinder&FAM=ARM7

- Automatic flag detection and insertion
- Automatic zero bit deletion and insertion
- Automatic Frame Check Sequence (FCS) generation and check (CRCCCITT)
- Abort detection and transmission
- Idle detection and transmission
- 32 Maskable Private Address bits field recognition
- 4 single byte Maskable Group Address field recognition
- Check of the integer number of bytes received in a frame
- Up to 16-bit programmable preamble sequence
- Up to 16-bit programmable postamble sequence
- Two independent input clock lines (one in reception and one in transmission)
- NRZ,NRZI,FM0 and MANCHESTER modes both RX/TX
- Digital Phase Locked Loop (DPLL) for clock recovery
- Capability to complement input/ouput frame.
- Local loopback mode
- Autoecho mode
- Full Duplex operating mode
- Interrupt operating mode
- 2x128 byte RAM buffers for transmission and reception

 

[onioni]

opencores fm0

Try PMC 7367.