look at my vhdl, why it doesn't work after synthesis

[paradbird]

I want to do asynchronism write, but this program can't work after synthesis, I don't know why. Please give me some advise. Thanks a lot.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ioInput is
port(
D_out1 : out std_logic_vector(255 downto 0);
D_out2 : out std_logic_vector(127 downto 0);
cs : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(3 downto 0);
D_in : in std_logic_vector(31 downto 0)
);
end ioInput;

architecture arch_ioInput of ioInput is

subtype SLV32 is std_logic_vector(31 downto 0);
type tmp_Data_in_type is array (11 downto 0) of SLV32;
signal tmp_Data_in : tmp_Data_in_type;

begin

process(cs,addr,wr,D_in)
begin
if cs = '0' and wr = '0' then
case addr is
when "0000" => tmp_Data_in(0) <= D_in;
when "0001" => tmp_Data_in(1) <= D_in;
when "0010" => tmp_Data_in(2) <= D_in;
when "0011" => tmp_Data_in(3) <= D_in;

when "0100" => tmp_Data_in(4) <= D_in;
when "0101" => tmp_Data_in(5) <= D_in;
when "0110" => tmp_Data_in(6) <= D_in;
when "0111" => tmp_Data_in(7) <= D_in;
when "1000" => tmp_Data_in(8) <= D_in;
when "1001" => tmp_Data_in(9) <= D_in;
when "1010" => tmp_Data_in(10) <= D_in;
when "1011" => tmp_Data_in(11) <= D_in;

when others => null;

end case;
end if;
end process;
D_out2 <= tmp_Data_in(3) & tmp_Data_in(2) & tmp_Data_in(1) & tmp_Data_in(0);
D_out1 <= tmp_Data_in(11) & tmp_Data_in(10) & tmp_Data_in(9) & tmp_Data_in(8) &
tmp_Data_in(7) & tmp_Data_in(6) & tmp_Data_in(5) & tmp_Data_in(4);

end arch_ioInput;

 

[rntsay]

code looks reasonable, maybe it's your synthesis tool. I know synplicity has trouble with "&" sometimes.

 

[arena_yang]

As I can see, the total number of the input and the output pins is very large. So If this module is used as a top level of a design ,pls check the max available io pins of the device you selected.If the max io number is less than the number you used here, it will not work correctly.

BTW, if there is a clock signal in your design, pls modify this module to synchronus design, otherwise, it will have a long logic trace delay! Keep in mind that VHDL is a HARDWARE language

 

[rntsay]

why would he want to add a clock to his design? (old synchronous design dogma!) he specifically says this is an asynch design...he's decoding/muxing which is fine the way he has it.

 

[maestor]

Hi,

Do you get any warnings, errors after synthesis?
What synthesis tool are you using?
What device/technology are you targeting?

About the clock, I think you can not guarantee that your outputs are going to be estable, all of them, at the same time, altough I see that you are only changing 32 bits per write. And, of course, depends of the downstream device which is sampling them, and also depends of how fast you toggle your inputs.
With a clock is EASIER to perform a timing analisys and constraint your design but if you don't want to use a clock you'll have your reasons.

As arena_yang said if this module is used at top level you need a device with a number of user IO pins > 422.

Regards,
-Maestor

 

[homeadd]

Whether the actual input "D_in" in you design satisfy with the setup time?In general,the data will be latch into register at the rising edge of wr.

 

[maniasonic]

please check your synthesis constraint script first. because if you make wrong constraints, the synthesizer will produce false result.

always remember, it's the designer, not synthesizer, who is responsable of the correctness of the design.

 

[honey]

please check your synthesis constraint script first. because if you make wrong constraints, the synthesizer will produce false result.

always remember, it's the designer, not synthesizer, who is responsable of the correctness of the design.great

 

[Al Farouk]

The VHDL construction seems to be correct. if you mean that the design dos not work in real world be carefull to to check the control signal supplied to your design (CS, WR, address, data) it should be clean signals as your design is compinational any change (nois) in any signal will change the output. to check wether the error due to design or due to the signal supplied add an input (manual clock) that the operation of the design is done with this input change and check the expected output with each edge if it wirk correct, then the error due to the signal supplied otherwise du to design error

 

[elektrom]

Another way to write is to using rising edge of WR signal. Like this...

process(wr)
begin

if wr'event and wr = '1' then
if cs = '0' then
case addr is
...............

This style is suitable for FPGA architecture.

 

[r_e_m_y]

hi,

I agree with elektrom. You must add a clock signal if you want to memorize some data in registers. The synthesizer will do it with the signal='1' and signal'event code. If not, the synthesizer will never latch your data... it will only make logic.

 

[shawndaking]

I Think This Is Too Ambigous Code Tring to Mux 32 bit to So Many latches. Mabee You Need To Implement It On Large FPGA (VIRTEX2)
Or In A Different Way !