Hi,
I want to design a power detector which can monitor the received signal power. I know one implementation is to use piece-wise linear proximation of the logarithm function by using a cascade of limiting amplifiers, which can be implemented with CMOS process.
If I don't want to use cascade of limiting amplifiers(which is too current consuming), I want to implement it just to detect the received input signal directly and logrithmic full-eave recitify and low-pass filter it to get the RMS power voltage. I have the difficullties in the logrithmic fuction implementations in cmos process.
Can any one have any good ideas?
Thanks in advance
Regards
John