-= Logic Synthesis & STA =-

Hello All,

What steps are usually used for fixing timing violations after first-run synthesis? Let's say that all the boundary constrains were applied and clocks defined.

Should the asynchronous reset/set lines be checked for setup/hold violations?

That corners are usually used for for the STA analysis? Are there exceptions? Why? What's about the typical delays corner? When should it be used?

Thank you!

Increase the clock period to remove set up time violations. Check for multicycle paths and false paths. Filter both of these.

I am not sure about asynchronous signals.

Just try nominal case for STA first

dmitryl said:

Hello All,

What steps are usually used for fixing timing violations after first-run synthesis? Let's say that all the boundary constrains were applied and clocks defined.

Should the asynchronous reset/set lines be checked for setup/hold violations?

That corners are usually used for for the STA analysis? Are there exceptions? Why? What's about the typical delays corner? When should it be used?

Thank you!

Click to expand...

asynchronous set/reset can be taken care in HFN (high fanout) synthesis (buffering) later , during synthesis treat them as ideal network, check your sdc constraints
synthesis/ sta should be run on worst op conditions, typical corners you can check during post layout sta

Check if the worst path is real or not. If real, ask the designer if he could modify the structure to remove some logic..., if not real define a false path.

yes, first its important to check if it is a real path or not.
But i would also look if my constraints are well applied in case you missed an MCP or has the tool not used very complex cells to reduce the logic levels or it has not picked up very high delay libcells, used the fastest cells or not and if there was any room for improvement in logic structuring although did not etc.

chakra wrote: "typical corners you can check during post layout sta" - why it should be run on the typical corner at all? In the post-layout STA, should checks using the typical corner replace a run on the WC and BC corners?

As for the STA tools, are they able to make timing checks on the WC and BC corners on a single run or separate runs should be done for each corner?

As for the boundary constrains (input/output delays, clock definitions, etc), why are they not defined with min/max delays as well?

---------- Post added at 16:08 ---------- Previous post was at 15:56 ----------

rca wrote: "Check if the worst path is real or not" - what does it mean "real"? who should check it - a RTL designer or a Synthesis engineer? Does "real" means "functional"?


"ask the designer if he could modify the structure to remove some logic" - the RTL code is already functionally verified and the RTL manager refuses to change the RTL. His answer was "apply a max_delay constrain on the path". But the violated path is an internal one... Is it not enough to set boundary constrains (the design is flatten), should I also apply max_delay constrains on the internal paths? Will it help?

Thank you!

---------- Post added at 17:51 ---------- Previous post was at 16:08 ----------

What's MCP?

Yes real means functional

What about rest of the questions? Does anybody want to response?

for the reset/set line, it is recommanded to released the reset on the opposite clock edge.

MCP - multi-cycle path.
The idea to execute all corners STA is to ensure that the design will meet its frequency etc in all operating conditions.

I think in your case you need to debug the path properly for the violation.

Could you give me a scenario where timing violations happen on the typical delays and do not happen with min/man delays?

Is it possible that hold violations happen on max delays and NOT happen on min delays on the same Netlist? Would you provide please an example how does it happen?

Thank you!

it is very difficult to give examples in such cases also in most of the cases examples may not be handy..
if you already are facing some issue and if you share that .. it helps in answering...

Attached find a circuit with PLL. Assume that PLL is analog and in the Netlist it just an empty module. In the practice, it has the known jitter and latency.
So, how should I define this circuit. What are the constrains?

Thank you!

Any response?

dmitryl said:

Any response?

Click to expand...

@Dimitryl: queries you had on corners, for complex design and pvt derates it becomes mandatory for sign-off to check paths with typ corners as you could see hold violators especially on dft mode which may not be indentical to bc-wc

dmitryl said:

Attached find a circuit with PLL. Assume that PLL is analog and in the Netlist it just an empty module. In the practice, it has the known jitter and latency.
So, how should I define this circuit. What are the constrains?

Click to expand...

Assumption, CLK1 is test clock. Mux infront of PLL has TEST_EN (port) as a selector that will bypass clock output from PLL and output CLK1 in test mode.

Now, you will need two constraint, one for functional mode when PLL clock is used and the other for test mode when CLK1 is used.

Functional_SDC

set_case_analysis 0 [get_ports TEST_EN]

create_clock -name PLL_CLK -period xx -waveform {0 x} PLL/CLKOUT
set_clock_uncertainty -setup xx [get_clocks PLL_CLK]
set_clock_uncertainty -hold xx [get_clocks PLL_CLK]

create_clock -name CLK1 -period xx -waveform {0 x} [get_ports CLK1]

create_generated_clock -name FUNC_CLK -source PLL/CLKOUT -divide_by xx [get_pins mux0/Y]


set_input_delay -clock FUNC_CLK xx [get_ports IN1]
set_output_delay -clock FUNC_CLK xx [get_ports OUT1]
set_output_delay -clock FUNC_CLK xx [get_ports OUT2]

set_input_transition xx [get_ports IN1]
set_load xx [get_ports OUT1]
set_load xx [get_ports OUT2]

set_max_capacitance xx [current_design]

set_max_delay xx -from [get_ports IN1] -to [get_ports OUT1]


Test_SDC

set_case_analysis 1 [get_ports TEST_EN]

create_clock -name CLK1 -period xx -waveform {0 x} [get_ports CLK1]
set_clock_uncertainty -setup xx [get_ports CLK1]
set_clock_uncertainty -hold xx [get_ports CLK1]

create_generated_clock -name TEST_CLK -source [get_ports CLK1] -divide_by xx [get_pins mux0/Y]

set_input_delay -clock TEST_CLK xx [get_ports IN1]
set_output_delay -clock TEST_CLK xx [get_ports OUT1]
set_output_delay -clock TEST_CLK xx [get_ports OUT2]

set_input_transition xx [get_ports IN1]
set_load xx [get_ports OUT1]
set_load xx [get_ports OUT2]

set_max_capacitance xx [current_design]

set_max_delay xx -from [get_ports IN1] -to [get_ports OUT1]