logic ofDriving compatability between DS1110S and 74ABT04

The DS1110S can usually drive logic levels suitable for devices like the 74ABT04 without needing an additional pull-up resistor, given the lower input capacitance and the drive capability of the DS1110S.

Hello, I am interested in the math logic:
1.what is the capacitance of typical 74LS device?
2.How can i see that it doesnt need the pullup threw the I=C*dV/dt formula?
Thanks.

Update:
My load capacticance (input of the 74ABT04) is 3pF
I need to deliver a pulse so it will reach V_IH.
pullup current of the DS1110S is 1mA.
my pulse width is 200ns with 10ns rise time so from the formula I=C*dV/dt
1mA=3pF*(X/10ns)
X=3Volts
so its enough.
The question is what do we do if we dont reach VIH value.
How pullup resistor can help use increase the pullup current?
Thanks.

yefj said:

Hello, I am interested in the math logic:
1.what is the capacitance of typical 74LS device?
2.How can i see that it doesnt need the pullup threw the I=C*dV/dt formula?
Thanks.

Click to expand...

The math for TTL is always based on Io/Iin current ratios = 10 for the same TTL family and not based on capacitance. The input current is expected to be < = 15 pF (std) / 10 = 1.5 pF which is normal to be less than CMOS.

It is always with an input threshold of two Vbe drops or 1.4V nominal at room temp. which happens to be the average of Vil + Vih. (0.8+2.0) to cover extreme temperatures and tolerances.

The math for CMOS is based on Vol/Io = Zo for a driver to Vih min/max with "T" family being TTL compatible threshold ( average of 0.8 and 2.0) . No need to worry about Voh .

Thus driver impedance and load capacitance directly affect risetime.
The 74LS has 120 + Rce (<5) for Zoh to Cin = 3pF, thus Tau= RC= 450 ps thus for a

For the LS family 400 uA/ 40 uA = 10 same as DS1110 delay line

For the risetime from TTL to CMOS you might use the specs Ic = 400 uA , C = 3 pF and Vih = min = 2V for 74ABTxx but in reality, it depends Darlington hFE, 8k Rb from 5V and a rising Vout for declining current which starts by exceeding -400 uA. (-15mA min)

I believe the 5ns/V CMOS input slew rate limit is to avoid transition noise producing multiple output transitions. This may be marginal but I think OK.

For CMOS the input current, Iin is only 1 uAdc + CdV/dt =3pF*dV/dt max due to gate leakage.