logic gates using klayout

how to design layout for logic gates using klayout....is anybody working on klayout? any videos please ....

I've used it, made some gates (up to DFF complexity) on a 180nm CMOS flow (shuttling back & forth from / to Cadence via GDSII). There's nothing unique about klayout, it's just a nice layout editor.

What you probably want, is material about how to design standard cells such that they are routable yet compact. That's not really layout-tool-specific, although P&R tools may inform how you like to place pins, row height, interior routing channels and compatibility with routing grid (if any), target features for router and so on.