I have a logic gate, in which recommended VCC is min. 4V and max. 5V.
can (I) operate the same logic gate at 3V and get my desired results?
Let me suggest some rules for logic with unstated expectations
1. Never assume if one gate works another will too. Always conform to specs otherwise, the unexpected may happen ( Murphy's Law) There is some variation within a process and also depending on channel size and factory wafer doping process, some speed variations, so it you do not follow "Worst Case" Rules for timing, your design may become the "worst case".
( In the old days ( 70's) if a chip wasn't fast enough ( {"for our desired results"}, we would check if it was Motorola and disqualify them from that part list and only use Fairchild. If it still wasn't fast enough, we'd raise the voltage and still not fast enough, we'd put cold spray on it. ( but that is just for experience, not final design)
Operating below the rated voltage limits means none of the specs are guaranteed, so if your logic dictates, does it toggle, maybe it will, but will it have it be slower, worse unequal slew rates or have much less noise immunity....? or all of the above? Probably.
There are at least 13 different active logic families each with different voltage ranges. None of them have 4 and 5V for min/max.
The lowest driver impedance and fast I have found are on the ARM chip with 25 Ohms ESR on the 3.3V drivers. Old HC4xxx CMOS is usually around 200~300 OHms. You may not care but load & stray capacitance x driver ESR, both affect rise time. If you are doing a lot of synchronous clocking, you have to watch for race conditions with worst case timing. NOrmally a timing analysis was done manually on all production designs. Now they have simulators with Monte Carlo analysis on power consumption and timing etc.