[Logic Design] Signal Processing Interview Questions

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ivlsi

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Hi All,

Please post Interview Questions on the Signal Processing subject for Logic Design Engineers.

Thank you!
 

That is such a vague, broad question that it is almost meaningless. What kind of answer are you expecting? What kind of job are you applying for? VOIP? Pro Audio? Video processing? Consumer products? Military applications?
 

Signal Processing Logic Design Engineer (mainly Image and Video processing).

e.g. Fourier Series implementation -> how to implement in hardware?
 

I'm not a big DSP guy, but I think you can probably expect questions about your background in ASIC or FPGA design; what tools you've used; what devices you've targeted; VHDL/Verilog knowledge; what algorithms you've implemented or are familiar with; how you would do debugging. You might expect a question about a specific problem, for example data compression, and how you'd approach it.

Basically, I don't think you can 'study' for an interview other than knowing what the specific company does and what they are looking for. Either you know your stuff or you don't. If you're interviewing for a position that involves video processing you might want to review 2D image processing, but I wouldn't worry about control systems.
 
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    ivlsi

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I see, thanks Barry. Do you know specific problems (even without exact answers), which are related to image processing?

BTW, do you know how to solve/eliminate turn around cycles while accessing synchronous memories (switching between read and write cycles). could it be solved to have zero turn around (I know it can, but I don't know how)?
 

I don't really have any image problems for you.

As far as turnaround cycles, that's a function of the memory device, not anything you can control. That's why they make ZBT (zero-bus-turnaround) SRAM.
 
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    ivlsi

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As far as turnaround cycles, that's a function of the memory device, not anything you can control. That's why they make ZBT (zero-bus-turnaround) SRAM.
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So, for ZBT memories, can I change values on the Address Bus each clock cycle without considering of the access type (read or write)?

Do you know how ZBT is implemented inside of the memories? Should they be pipelined memories?
 

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