Lock-up Latch Question

My design has four clock domains( functional freq coming from PLL 250MHZ, 150MHZ etc), but during the shift mode, all the scan chains use low frequency 20MHZ. In this case, do I need lockup latches since the shift freq is same for all the flops in all domains? Only in the functional mode (at speed capture) uses high freq clocks.

The lockup latch should be inserted no matter how low the frequency is to make sure there is no hold violations between async registers in the scan chain.

My question is if all the flops in the design are running at same shift clock say 20MHZ. In that case, do I need lockup latch? Lockup latch is used to prevent hold time violations caused by two different clock domains during shifting. In case if the shifting is same clock for all flops, do I still need lockup latches. During capture it uses PLL freq from different clock domains.

You have to consider "the length of clock tree"

In the other words, the hold time violation will occur for the flip-flops with same clock source if the clock tree are not balanced.
Also, same clock frequency with different phase may cause this problem too.
Therefore, you have to do timing analysis ( during both APR/signoff phase) during the scan mode to ensure the correctness of scan shift.

Back to our question, you don't need to insert lock-up latch.
But you have to do static timing analysis to guarantee the balanced clock tree instead !!!
If there is asynchronous/unbalanced path during scan shift, the timing violation will be reported if constraints is correctly issued.

Regards,
Polo

I think if you have negative edge flops talking to positive edge ones, then lockup latches should be automatically inserted by the synthesizing tool to prevent data shift through both the flops in one clock cycle. This will precisely prevent the hold violation the capture flop.

Hi,

Lock up latches are inserted in the design to avoid hold violations that occurs during scan shifting. In scan shift mode all the flops in the design are triggered by single clock. But in layout CTS will be driven by your clock frequency and clock_skew_groups.

When two clocks are not balanced at layout end we tend to see hold or setup violations between these two clocks as their skews are not balanced.

Suppose I have two functional clocks in my design which are Asynchronous and their scan shift clock is same. I prefer to build clock tree for my two functional clocks without balancing them, If I do balance them for the purpose of scan shift it which will result in increasing clock tree cells(increases power and area). So, placing a lockup latch between the flops which are triggered by asynchronous clocks for scan shift purpose can fix the hold violations.

~vamsi

Hi Vamsi,

Couldn't buy this statement ... "In scan shift mode all the flops in the design are triggered by single clock"

Please explain.

Hi Nandasan,

Usually in shift mode all the flops in the design will be triggered by a single shift clock which will be feed from tester.

At block level you may have different ports but at chip level all these clocks will be muxed with shift clock.

~vamsi