Loading a ELF file to Microblaze mem on ModelSim

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slutarius

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Hi,

I have a project using Microbalze on Vivado. I can point the software ELF file generated by SDK to the Vivado project and the simulation work fine on Vivado.
The problem is about running time is long, and I want to move the simulation to ModelSim.

On ModelSim, I can compile the same Verilog design with Vivado, the remain problem is about Instruction Code of MicroBlaze.
My idea is to find a method to convert C code or ELF file to HEX file. Then load the HEX file to MicroBlaze mem on ModelSim.

Is that a correct flow ?

P/S: I searched for a while on google but not yet an answer found. Still digging...

Thanks,
SLU
 

Is there a problem in using ModelSim inside Vivado not recognizing the ELF file generated by Xilinx SDK?
I don't know for sure if there is some procedure to make ModelSim recognize that, please look into the related docs/specs. I have never come across this use case in my work. The ELF file is generally associated with the uB, and when you supply clock after reset from the TB, the uB should execute the contents of the ELF.
I would look to this first as it would reduce your time to write code that is necessary to read in the hex file.

If the above can't be done, then you can go for the 2nd option. There should be commands in Xilinx to convert from elf to hex. Yes, I don't see anything wrong in the 2nd flow.
 
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Hi dpaul,

Thanks for the reply.

There is no problem if ModelSim running from Vivado when switching the simulator in Design Option.
The software can be run normally like Vivado simulator does.

But what I wonder here is about stand-alone ModelSim run, and we need to associate the software to MicroBlaze.
Can we do that ? and would the running time descreased ?
 

But what I wonder here is about stand-alone ModelSim run, and we need to associate the software to MicroBlaze. Can we do that ?
In my opinion "associate the software to MicroBlaze" is the work for Vivado, independent of the simulator s/w option. Just try it out.
Please inform me if you succeed....this would be some handy info!

and would the running time descreased ?
Can't comment on that.....don't know anythng about your model, design!
 


I will tell a little more about my runs:

Option 1: Vivado only
1/ Generate the software application by C code on SDK, SDK give out ELF.
2/ Associate ELF to Microblaze on Vivado. It is done.
3/ Run simulation by Vivado simulator or ModelSim simulator is OK. ( ModelSim is invoked when you switch the option from Simulation Settings on Vivado, see picture )

Option 2: ModelSim run separately from Vivado.
1/ Generate the software application by C code on SDK, SDK give out ELF.
2/ Associate the ELF to Microblaze instruction memory in ModelSim simulation. Vivado is closed, only ModelSim opened. (*)
3/ Run simulation by ModelSim. (**)

Questions:
For (*), Can we associate the ELF to MicroBlaze in ModelSim run ?
For (**), with the same design and ELF with Option1, is the simulation runtime faster than Option1 ?

 

I already gave you the answers as per my point of view. Again...

For (*), Can we associate the ELF to MicroBlaze in ModelSim run ?
Ans> In my opinion yes. Viv Main Menu > Tools > Associate ELF files (Just do it kepping ModelSim as the simulator).
If you face a problem after that do post it here.
As I already told you I have never faced this use-case, so just do it and see what happens!

For (**), with the same design and ELF with Option1, is the simulation runtime faster than Option1 ?
Ans> I don't know that. I have no methods or info to evaluate that. I can't say anything about it.
 

You misunderstood about (*), sorry for my poor explanation.


Forget the Vivado, can we associate an ELF file into a ModelSim run ?
 

There is no file association for the ELF file in Modelsim. If the simulation is run with an ELF file there has to be some VHDL/Verilog file that reads that ELF and populates the memory array used for the instruction memory of the uBlaze at time 0. You just need to make sure the location of the ELF is where the HDL expects the file to reside. I don't believe the file gets converted to another format for the simulator's use, but then I haven't messed around with simulating a uBlaze system for a decade, so this might have changed.
 
That means in the use case involving a uB and an elf file, if a simulator other than Vivado's is used, then the only flow to be used is to convert the elf to hex and then have the hex file read as instruction memory by the uB/uP?

btw- I had an idea that there are always some associated tool chains that allow conversion from elf to hex!
 

The elf file is a text file, so why would you need to change it from elf to hex?

TextIO functions exist in both VHDL and Verilog and can read pretty much any text file you might run across.

- - - Updated - - -

A search that I did seems to indicate that the tools will generate the initialization code for a .mem file and data2mem can be used to convert from an elf to a mem file.
 
The elf file is a text file, so why would you need to change it from elf to hex?
A search that I did seems to indicate that the tools will generate the initialization code for a .mem file and data2mem can be used to convert from an elf to a mem file.
I found the similar thing about using memory initialization from .mem to uB. Not a clear approach yet but will look it deepy today.
Thanks.
 

Sorry slutarius, don't want to hijack your post, but my doubt needs to be discussed here, as per ads-ee's comment.

The elf file is a text file, so why would you need to change it from elf to hex?
Because a hex file can be looked upon easily as an instruction memory by a processor that can be read by VHDL and Verilog.

An elf file is a standard binary format made up of one ELF header, followed by file data. Sure it is in text format. But it might be my ignorance or less experience, I have not see any processor reading directly an elf file.

A couple of years ago, I was working on the instruction set modification of a 32bit x86 based processor. For testing the uP core interfaces (SPI, IIC), I was writing simple C codes, which was intended to serve as fodder for the instruction memory of the uP. This is uP was implemented on Spartan6 and blocks RAMs were serving as the instruction memory.
Custom tool chains and Makefiles were provided using which were used to first convert my C code/s to elf/bin and then to hex format. The top-level Verilog file would just read-in the hex file and execute the instructions there in. This was all done for the simulation.

Xilinx provides SDK, which simplifies all these tool-chain usage, generates a bit file from a C file which can be directly associated with the uB using the Viv main GUI menus. So for someone using a uB based design, his headache for simulation is significantly reduced if the Xilinx Viv simulator is used.

A search that I did seems to indicate that the tools will generate the initialization code for a .mem file and data2mem can be used to convert from an elf to a mem file.
Exactly, but here the OP is only talking about simu (Modelsim).
For implementation, Xilinx tools were already there for embedding the elf into the bit file.
 
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Hi, Slutarius.

I'd like to use a stand-alone modelsim, too. becose, too quick start.

So, checked for running of modelsim at the Vivado environment.
generated the mem file at simulation start . (ex. IPBlockName_lmb_bram_0.mem)
maybe, convert from elt to mem file.

When there is this file, run simulation by C-program code.
(Copy mem file to modelsim project holder.)


modelsim project holder is below.
dir sim_1
dir work
file modelsim.ini
file my_cpu_lmb_bram_0.mem
file sim.cr.mti
file sim.mpf
file transcript
file vsim.wlf
file wave.do

but, I don't know the elf to mem convert command!
so, run modelsim on vivado simulation environment when changed elf file and
the mem file copy to modelsim project holder.

If there is a person who knows, please tell me.

Thanks,
Kyo
 

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